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JPS59168641A - Reactive sputtering etching device - Google Patents

Reactive sputtering etching device

Info

Publication number
JPS59168641A
JPS59168641A JP4254683A JP4254683A JPS59168641A JP S59168641 A JPS59168641 A JP S59168641A JP 4254683 A JP4254683 A JP 4254683A JP 4254683 A JP4254683 A JP 4254683A JP S59168641 A JPS59168641 A JP S59168641A
Authority
JP
Japan
Prior art keywords
dust
pattern
wafer
sample base
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4254683A
Other languages
Japanese (ja)
Inventor
Hiroshi Sano
洋 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4254683A priority Critical patent/JPS59168641A/en
Publication of JPS59168641A publication Critical patent/JPS59168641A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To remove the deformation of a pattern due to the adhesion of dust, and to improve the accuracy of the pattern by mounting a sample base turning a plurality of wafers to an upper section. CONSTITUTION:A gas introducing pipe 3 is connected to the central section of a cylindrical chamber 1 through a circular electrode 2, a sample base 4 with a wafer holder is disposed to the circular electrode 2 in the chamber, and air is discharged by an exhaust pipe 5 at the upper section of the sample base. Dust does not drop and adhere to a wafer 6 and the deformation of a pattern is prevented by turning the sample base 4 and etching the wafer on etching. According to the method, the quantity of dust is made smaller than conventional structure by half or less, and the deformation of the pattern due to dust can be reduced.

Description

【発明の詳細な説明】 本発明は反応性スパッタエツチング装置に係シ、特に半
導体装置の製造等に使用される反応性スパッタエツチン
グ等に用いられる乾式装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reactive sputter etching apparatus, and more particularly to a dry type apparatus used for reactive sputter etching used in the manufacture of semiconductor devices.

近年半導体基鈑の直径が大きくなる、かつパターンサイ
ズが微細化するにつれてエツチング中にてウェハーに付
着するゴミが問題となってきた。In recent years, as the diameter of semiconductor substrates has become larger and the pattern size has become smaller, dust adhering to wafers during etching has become a problem.

従来の反応性スパッタエツチング装置では、円形の試料
台の上に複数のウェノ１−を並べ、その試料台を下部に
有しエツチングする機構であるため、エツチング中にウ
ェハーへゴミが落下し付着するためパターンクズレが発
生するという欠点がある。In conventional reactive sputter etching equipment, a plurality of wafers 1- are arranged on a circular sample stage, and the sample stage is located at the bottom of the etching system, so dust falls onto the wafers during etching and adheres to them. Therefore, there is a drawback that pattern distortion occurs.

本発明は複数のウェハーが回転するところの試料台を上
部に有することを特徴としたもので、これによシゴミ付
着によるパターンクズレを解消しパターン精度を上げる
ことのできる反応性スパッターエツチング装置を提供す
ることができる。The present invention is characterized by having a sample stage on the top on which a plurality of wafers are rotated, thereby providing a reactive sputter etching apparatus that can eliminate pattern distortion due to dust adhesion and improve pattern accuracy. can do.

以下本発明の実施例を図面によって説明する。Embodiments of the present invention will be described below with reference to the drawings.

円筒状のチャンバー１の中央部には円形電極２を通して
ガス導入管３を接続し、チャンバー内には円形電極２に
対してウェハーホルダーを有する試料台４を配し、排気
は試料台上部の排気管５によって行う。エツチング時に
は試料台４を回転させエツチングをおこなうことによシ
ウェハ−６にゴミの落下の付着がなくなシバターフズレ
をふさぐものである。なおこの方法にてパターン精度は
従来の構造と比べるとゴミ量は半分以下となる。A gas introduction tube 3 is connected to the center of the cylindrical chamber 1 through a circular electrode 2, and a sample stage 4 with a wafer holder is placed in the chamber relative to the circular electrode 2. This is done by tube 5. At the time of etching, the sample stage 4 is rotated to perform etching, thereby eliminating the adhesion of falling dust to the wafer 6 and sealing the wafer sag. Note that with this method, the pattern accuracy is reduced to less than half the amount of dust compared to the conventional structure.

以上詳細に説明したように本発明の方法によれば従来の
装置に見られるようなゴミによるパターンクズレは低減
できる。As described above in detail, according to the method of the present invention, pattern distortion due to dust, which is seen in conventional devices, can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例の装置の断面図である。 尚、図において　１・・・・・・円筒状チャンバー、２
・・・・・・円形電極、３・・・・・・反応ガス導入管
、４・・・・・・円形試料台、５・・・・・・排気口、
６・・・・・・ウェハー、７・・・・・・ウェハーホル
ダー、８・・・・・・ＲＦｔ源、９・・・・・・バキュ
ーム口。 篤　／　図FIG. 1 is a sectional view of an apparatus according to an embodiment of the present invention. In addition, in the figure, 1... cylindrical chamber, 2
......Circular electrode, 3...Reaction gas introduction tube, 4...Circular sample stage, 5...Exhaust port,
6...Wafer, 7...Wafer holder, 8...RFt source, 9...Vacuum port. Atsushi/Figure

Claims (1)

【特許請求の範囲】[Claims] 複数の半導体ウェハーを並べるだめの試料台と、該試料
台を回転させる手段とを備えた反応性スパッタエツチン
グ装置において、電極を下部に有し、試料台を上部に設
けたことを特徴とする反応性スパッタエツチング装置。A reactive sputter etching apparatus equipped with a sample stage for arranging a plurality of semiconductor wafers and a means for rotating the sample stage, characterized in that the electrode is provided at the bottom and the sample stage is provided at the top. sputter etching equipment.
JP4254683A 1983-03-15 1983-03-15 Reactive sputtering etching device Pending JPS59168641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4254683A JPS59168641A (en) 1983-03-15 1983-03-15 Reactive sputtering etching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4254683A JPS59168641A (en) 1983-03-15 1983-03-15 Reactive sputtering etching device

Publications (1)

Publication Number Publication Date
JPS59168641A true JPS59168641A (en) 1984-09-22

Family

ID=12639051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4254683A Pending JPS59168641A (en) 1983-03-15 1983-03-15 Reactive sputtering etching device

Country Status (1)

Country Link
JP (1) JPS59168641A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5693238A (en) * 1993-05-03 1997-12-02 Balzers Aktiengesellschaft Method for improving the rate of a plasma enhanced vacuum treatment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5693238A (en) * 1993-05-03 1997-12-02 Balzers Aktiengesellschaft Method for improving the rate of a plasma enhanced vacuum treatment

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