JPS59168312A - Pattern-defect judging device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a pattern defect determination device, and in particular, a pattern defect determination device for determining the thickness of wiring patterns of printed circuit boards, semiconductor integrated circuits, etc. It is related to the device.

[Prior art]

Conventionally, methods for detecting defects in wiring patterns of printed circuit boards and semiconductor integrated circuits include (1) pattern comparison method; (2)
Defect feature extraction methods have been proposed. Among these methods, method (1) involves determining a defect by comparing a pattern generated from design data or an adjacent pattern with a pattern to be inspected, and method (2) determining the characteristics of the defect in advance and identifying it as a defect. The basic principle is to treat characteristic parts as defects. All of these conventional methods can only determine the position and dimensions of a defect within a pattern2, but have not reached the point of determining the fatality of the defect to the pattern.

[Purpose of the invention]

An object of the present invention is to provide a novel pattern defect determination device that can easily determine the presence or absence of a fatal defect in a wiring pattern or the like.

[Summary of the invention]

In order to achieve this object, the pattern defect determination device of the present invention stores in advance the number of normal patterns in the inspection area, and compares it with the number of patterns to be inspected. use

In this way, if the pattern is completely short-circuited or disconnected, the number of putters/clumps will increase or decrease, so you can determine their existence by comparing it with the number of normal patterns stored in advance. can. On the other hand, if there is a half-short (thick) or half-broken line (thin) in the pattern, the pattern can be enlarged or reduced on the image depending on the tolerance level. 1. [Embodiments of the Invention] Hereinafter, the present invention will be described in detail with reference to Examples. N1
The figure shows an example of the overall configuration of the defect determination device of the present invention. 7 is a computer (cpU) that controls the entire system;
The inspection object 8 is placed on an XY stage 5 whose position is controlled by a control signal 7a. Reference numeral 6 denotes a timing signal generation circuit, which is activated by a control signal 7a and supplies timing signals 6a, 6b, and 6C to each circuit. The pattern of the inspection object 8 is raster-scanned by the imaging device 1 in synchronization with the synchronization signal 6a, and becomes a video signal 1s. This video signal IS is sampled by a basic clock signal 6b by a pattern extraction circuit 2 consisting of a double-stranded circuit, etc., and converted into a pattern signal to be inspected 2S by being binarized. The determination circuit 3 is related to the present invention! D, (The test pattern is processed in the inspection area indicated by m number 6c. After scanning the inspection area, the absence of defects is read by the computer 7 as a signal 3S and displayed on the n1 display device 4 as a defect determination result 7b. Is displayed.

First, the principle of pattern defect determination in the determination circuit 3 will be explained. FIG. 2(1) shows a normal pattern, in which there are two patterns A and B as a cluster within the inspection area H. (2) and (3) show a complete short circuit and a complete disconnection, and the number of patterns is one (A') and three (A'), respectively.

B/, n//> depends on the change. Therefore, by comparing the numbers, that is, by changing the number from two to one and from two to three, it is possible to determine whether there is a complete short circuit or complete disconnection in the pattern. FIG. 3(1) shows a case where there is a half-open line C in the pattern AI and a half-short D in the pattern Bl. It can be seen that (3) is a reduction or enlargement of the pattern (1) (by reducing or enlarging the pattern an appropriate number of times), it can result in a complete disconnection or a complete short circuit.

A method for reducing and enlarging a pattern will be explained using FIG. 4 (5). Figure 4 shows an example of a binarized wiring pattern, and here the wiring pattern part is t I
n, and the other portions will be binarized and displayed as tl O71. From this binary pattern, partial patterns each having a size of 3 x 3 pixels as shown by the dotted line in the figure are sequentially cut out while shifting the position one pixel at a time in the x and y directions to construct this partial pattern. When signal processing is performed so that the output signal becomes '1'' only when all nine picture elements are in state II I II, xy
A binary pattern shown in (B) that is reduced by one pixel in each direction can be obtained. In case of pattern enlargement,
This can be realized by inverting the input binary pattern at l''at On ((after performing the above processing, the obtained signal °t II) II OII again. In this case, the number of pixels to be reduced or enlarged is the remaining dimension to1 of the defect C and D occurrence area in FIG.
The interval td is determined in advance depending on how far the interval td is allowed. For example, if the number of reductions is N1 and the number of enlargements is M, if the remaining size on the pattern to be inspected is 2N pixels or more, or if the distance between adjacent patterns is 2Ml [iii pixels or less, then , In state (3), it will be determined that the wire is disconnected or shorted.

Next, an example of a basic method for determining the number of pattern clusters will be described. This can be easily achieved by determining the so-called Euler number. The Euler number E is obtained by determining only the shape of the boundary of the two-dimensional putter 7 (7), and in the case of a pattern without internal holes, it matches the number of patterns as a cluster.

The method for determining Euler's number E is expressed by the following equation.

n[]B on the right side represents the number of digital patterns shown in ('3.Here, the 2〈mark is 1.0
Show that either is fine. The fifth section shows the cases of several patterns, outside the pattern is 01, inside is 1
It has been digitized in this way. In each case, the 2×2 pixel area indicated by the dotted line in the figure)
By sequentially cutting out the patterns, determining whether they match the pattern in the above formula or not, and counting the number of patterns,
The Euler number can be detected as shown in the cloth in the figure. Therefore, by determining the Euler number E for each of the previously determined contracted pattern and expanded pattern, the number of patterns as a group can be easily detected. Furthermore, by comparing these values with the original number of normal long turns, it is possible to determine whether the Shibata turn is thin or thick.

FIG. 6 shows an example of the circuit configuration of the determination circuit 3 embodying the principle described above. In the figure, 2S
is the diagonal pattern output from the pattern extraction circuit 2 in FIG. This turn signal 2S is transmitted to an enlarged circuit 3 consisting of a shift register and a judgment logic circuit, which will be described later.
After being enlarged by the necessary number of pixels by 1, it is input to the number counting circuit 33. The number counting circuit 33 consists of a shift register, a determination logic circuit, and an up/down counter as will be described later, and uses the method described above to process the signal 6.
The Euler number E of the enlarged pattern within the inspection area indicated by C, that is, the number of patterns is detected.

The comparator 35 compares the contents of the up/down counter in the number counting circuit 33 with a predetermined constant STH at the timing of the end of the inspection by the signal 6C, and if the value is small, it indicates that a short circuit exists. is notified to the CPU by signal 3S.

On the other hand, the determination of thinning (broken wire) is as shown in the flowchart in Figure 6.
This is done in the same way as the thickening determination. That is, the binary pattern 2S is reduced by the necessary number of strokes by the reduction circuit 32, and then,
The number of patterns is counted by a number counting circuit 34,
The value is compared with the constant LTH by the comparator 36, and if it is large, the signal 3S indicates that there is a thinning (cut M).
This is to notify the CPU.

Next, the specific configuration of the reduction circuit 32 will be explained with reference to FIG. This circuit consists of multiple stages of reduction units 32a to 3211 connected in series. As explained above, the number of stages of this unit is determined in advance based on the allowable remaining size interval of defects. Each unit includes two shift register coloring circuits 320 for cutting out a partial pattern of 3×3 pixels, and a determination logic circuit 321 for determining the partial pattern. The cutting circuit 320 is
For example, as shown in FIG. 8, two shift registers 322 can temporarily store binary information for one horizontal scanning pixel.
, 323, and 2-bit length shift registers 324, 325, and 326 that can temporarily store partial patterns. Then, the outputs a1 to a9 are 3× as described in FIG.
This becomes a binary signal of a partial pattern P of three pixels. The judgment logic circuit 321 consists of an AND gate, and receives binary signals a1~
If a9 is all It, 74, output signal t+,
17 is output. With the above configuration, the above-described reduction method can be implemented. As described above, the expansion circuit 31 can be implemented by adding one or more inverters to the input and output sections of FIG. 9.

FIG. 9 shows an example of the configuration of the number counting circuit 34. This circuit consists of a circuit 340 consisting of one shift register for cutting out a 2×2 partial pattern, and a logic circuit 341 for determining the bit arrangement of the partial pattern.
-1. -2. -3°-4 and their respective output signals 34
It is composed of up/down counters 342-1 and 342-2 that increment or decrement the count by 1-18-28, -38, and -48. Note that the operation of the Q up/down counter is controlled by a signal 6c indicating the inspection area, so that it can operate only within the inspection area. For example, as shown in FIG.
It consists of one shift register 344 that can temporarily store binary information for horizontal scanning pixels, and V rasters 345 and 346 that can temporarily store partial patterns. Then, the outputs b1 to b4 are binary signals of the 2×2 pixel partial pattern Q described in FIG. Therefore, it is sufficient to implement a circuit that outputs an output signal only when the partial pattern Q is a bit pattern indicated by the first to fourth terms on the right side of the equation for determining the Euler number E described above. These are decision logic circuits 1 to 4, and AND gates 347 to 35 as shown in FIG.
0 can be easily configured. In this way, the counter 342-1 calculates the first and third terms of Euler's equation.
When the term pattern is input, the count is incremented or down, and the counter 342-2 corresponds to when the second term pattern and the fourth term pattern are input. By shifting the values of these counters by one bit to the right, i.e., inputting them to the adder 343, the Euler number E, that is, the number of patterns, is determined.

The number counting circuit 33 in FIG. 6 can also be realized with a completely similar circuit configuration.

〔Effect of the invention〕

As explained above, the present invention stores the number of normal patterns tb in the inspection area in advance, determines the reduced pattern and enlarged pattern of the wiring pattern at the time of inspection,
This method is characterized by checking the number of patterns in each inspection area and determining the pattern measurement and thickness, so defects that exceed a predetermined fatality limit can be easily detected and This is an extremely inexpensive and effective device for making judgments.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of an inspection device that can employ the pattern defect determination of the present invention, the second box and FIG. 3 are diagrams for explaining the present invention in detail, and FIG. FIG. 5 is a diagram for explaining the reduction method, and FIG. 5 is a diagram for calculating Euler's number E using the Yuzu pattern. FIG. 6 is a diagram for explaining a specific example of the determination circuit 3 according to the present invention shown in FIG. Figure 7
This figure is a diagram for explaining a specific example of the reduction circuit in FIG. 6, FIG. 8 is a diagram for explaining a specific example of the extraction circuit and determination logic circuit in FIG. 7, and FIG. 6 is a diagram for explaining a specific example of the number counting circuit 34, and FIG. 1O is a diagram for explaining a specific example of the cutout circuit and determination logic circuit in FIG. 9. 1... Imaging device, 2... Pattern extraction circuit, 3...
・Judgment circuit, 4...Display device, 5...XY stage, 6...Riton 1 Kuchi IS 2nd section Figure 7 Figure 8

Claims (1)

[Claims] 1. In a device that detects and determines the width and fineness of a pattern, scans an area that includes the pattern, and
III. A first means for obtaining an image with a background of 0'';
a second means for obtaining each of the reduced and enlarged patterns of the pattern; a third means for respectively counting the number of reduced patterns and the number of enlarged patterns in the area; and comparing these numbers with a reference number. A pattern defect determination device having a fourth means, which determines that thinning exists when the number of reduced patterns is greater than the reference number, and that thickening exists when the number of enlarged patterns is less than the reference number. .