JPS59167116A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To realize an A/D converter which is very small-sized and has a high resolution and a high conversion speed by providing plural rows of charge transfer devices, which are different in value of storage gate capacity, in parallel and charging the electric charge repeatedly to generate an accurate reference voltage in a high speed. CONSTITUTION:A primed signal electric charge is sent to a sample holding buffer 111 provided for each vertical signal line or every several vertical signal lines at least and is compared with a reference voltage. The signal sent to a comparing part in this manner is compared with the reference voltage, and a high-1evel voltage (or pulse) is outputted to a signal line 112 when the reference voltage crosses the signal voltage. Signal lines 118, 119, 120, and 121 correspond to (00), (01), and (11) respectively. For example, when the high-level voltage is outputted to the signal line 112 in the process of determination of upper two bits, it is transmitted to a signal line 120 through a gate 116, and signal (1,0) is sent to the output side. simultaneously, a signal 121 is fixed to the low level by a gate 126, and therefore, the signal is not transmitted to the signal line 121 even if a gate 117 is opened.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is directed to converting an analog signal, which plays a central role in a signal processing device that takes in an external signal, converts it into a digital signal, and performs signal processing, into a digital signal. Device to convert (
(hereinafter abbreviated as A/D conversion device).

[Prior art]

FIG. 1 shows the general configuration of a device that inputs an external analog signal 6, converts it into a digital signal, and processes this signal. In the figure, 1 is a transducer such as an optical sensor, 2 is a preprocessing device, 3 is an A/D converter, and 4 is a transducer such as an optical sensor.
・ is a signal processing device, 5 is an external output device (controller,
CRT, etc.).

Since such a device performs digital signal processing, it is relatively easy to integrate the signal processing section into an IC, and a compact and multifunctional system can be constructed.

In such devices, once the input signal is converted into a digital signal, the noise introduced during the signal processing process can be almost ignored, so the signal-to-noise ratio (8/N ratio) is It is almost determined by the equipment, processing equipment, and A/D conversion equipment. For this reason, new devices are being developed with special attention being paid to these parts of the device. Among these, the signal conversion device is a particularly important part because it determines the signal resolution of the system, but as the processing speed increases to medium to high speeds exceeding 100KH2, power consumption and device size increase. It is often an independent device for reasons such as .

However, if a small, low-power A/D converter can be formed on a single chip at the same time as other parts, such as a transducer or preprocessor, the overall system size can be reduced and the range of applications can be expanded. This expansion will have an immeasurable effect, and it will be a major step toward the realization of a one-chip signal processing system.

As an example of integrating a small A/D conversion device with other functional parts, there is a case where a charge transfer element is used in a multi-level memory. (If you look at it, L, M.

'perman et, at, IEEE, J
, 8o1id-stateCirautS, 5C-16
, 5, pp 472-478゜oct, 1981,
(Japanese Patent Application Laid-Open No. 54-77582) However, the resolution (number of bits) of the A/D converter used for this is low (2 to 3 bits or less), and it is impossible to fill the gap.

Bipolar transistors are generally faster in processing speed for semiconductor devices, but in terms of multi-functionality, MC
8) The use of transistors is superior in terms of power consumption, element size, and functional diversity, and currently, LSIs using MC8) transistors are the mainstream for multifunctional semiconductor devices.

A/D conversion devices are broadly classified into parallel type, successive approximation type, and integral type.

Even with the MC8 type A/D converter, if you use the parallel processing type, you can process medium to high speed signals with a resolution of about 8 bits.
Ru. (For example, A, ]) ingwall.

IEEE, ]) igest of Technica
l papers of I8SCC, pp12'6.
1979. Also, Fujita et al., National Conference of the Institute of Electronics and Communication Engineers, Proceedings pp2-172. March 1981. ) However, these devices are large in scale (chip size) and are not suitable for mounting various devices on the same chip.

An integral processing type A/D converter (for example, K.

)(areyama et, at, IEEE, D
jgeSt ofTechnical paper
of l8SCC, pp184゜1979 and E, Ma
suda, IEEEI ]) igest ofTec
hnical papers of l8SCCe
Examples are given in, for example, pp 134+1978. ) is small in scale and easy to form on the same chip as other functional devices.

This type of memory is used in the multilevel memory mentioned above.

However, although this type of device can achieve high resolution, the conversion speed is limited to a few KH2, and high-speed signal conversion is impossible.

A successive approximation type A/D converter is relatively small in size and has a medium conversion speed. (For example, J, MCCr
early and P, RoGraYI IEEE
.

]）Igest of Technical pa
pers of l5SCC.

ppas, 1975. An example is shown in . ) However, as you can see in the above example, if you try to use the reference capacitance, which is a feature of the MC8 type A/D converter, to generate a reference voltage, and create a high-precision, low-power device, 8
In the case of Pitt, Co is the minimum capacitance value, and Co is 200
,400,16CO.

It is necessary to provide eight types of capacitors: 64CO, 128Co, and 256Co, and the ratio of the maximum to minimum capacitance is 256 times (corresponding to an 8-bit resolution level), so a large area is still required, and one The current state of the art has not yet effectively implemented such a device together with other functional devices on a chip.

[Object of the Invention] An object of the present invention is to provide a small A/D modification device that can be integrated with other functional devices in the system on one chip, thereby making it possible to extremely reduce the system scale. Torororu.

[Summary of the invention]

In order to achieve the above object, the present invention utilizes the high speed and high charge control accuracy of charge transfer elements and uses them in parallel to realize a compact A/D conversion device. This compact A/D converter is suitable for multiple use in parallel on one chip, and parallel signal processing realizes a highly practical A/D converter that can easily process even high-speed signals with high accuracy. can.

[Embodiments of the invention]

The present invention will be explained below using examples.

FIG. 2 is a diagram showing the overall configuration of the A/D conversion device according to the present invention. In the figure, 11 is a sample and hold section for input analog signals (hereinafter referred to as SLH section), 12 is a buffer section, 14 is a reference voltage generation section, 13 is a buffer section for reference pressure, 15 is a pulse generation section for supplying to 14, and 18 is 15
16 is a comparison section, and 17 is an encoder that generates a digital output.

FIG. 3 shows an example of a conceptual circuit diagram of the base voltage generating section 14 and buffer 15 in FIG. 2 in the case of a resolution of 8 pits.

In the figure, numeral 21 is a buffer circuit using a source follower, but even if this is not a source follower but another circuit, it has nothing to do with the essence of the present invention. 23 to 30 are charge transfer elements, which have a storage capacity of 23.27 and a capacitance of 32.36.
If O, the white circle in the middle of the accumulation is the terminal that applies the pulse,
The black circles are terminals to which DC voltage is applied, and the horizontal lines 32 are terminals to which high-level DC voltage is applied. This symbol is the same in other figures below.

The operation shown in FIG. 3 will be explained using FIGS. 4 and 5.

FIG. 4 (0 shows the charge transfer device shown in FIG. 3 23.27. Also, (a) shows the pulse timing applied to the terminals 41 and 42. (b)
43 is a charge injection terminal, 44 is a reference screw pressure generation terminal, 45 is a charge absorption terminal, and 40.31.3 in FIG.
2, and are formed of, for example, an n-type semiconductor layer. 46
．． A DC voltage is applied to 47. Further, potential differences between the gates 48 and 49, and between the gates 50 and 51 are given by different threshold voltages.

Figures 4(c)-(f) are potential diagrams showing that a precise constant charge is injected into and removed from terminal 44. The horizontal axis direction corresponds to the position of each electrode (FIG. 6(b)). (However, the lower side of the potential is in the positive direction, that is, the potential diagram is for electrons.) At fzt=to, φPI
, φDi are both at a low level, and no charge exists under the gate of the charge transfer element.

Further, 44 has been reset and is in the high arousal position (in the forward direction) ((C) in the same figure). When φP1 becomes high level at t=tl, charge is injected into gate 48.49, and at j=i3, φP1 goes to low level and gate 48.
．． A charge Q corresponding to the potential difference ΔVB below 49! is taken under the gate 49 (FIG. 4(d)). If the capacitance of the gate 49 is CO, then Q1=ΔVB-Co.

When φPi becomes completely low level (t=ta), the charges flow into the node 44 (FIG. 4(e)). When removing charges (1=14~ts), a constant charge Q1 is taken out from the node 44 in a similar process ((f) in the same figure). Here, Ql is a quantity that depends only on the potential difference ΔVB under the gate and the gate capacitance CO, so if these values are given accurately, for example, '
It is possible to inject and extract the amount of electric charge with high accuracy, regardless of fluctuations in the source pressure.

FIG. 5 is a diagram showing the operating principle of the reference voltage generating circuit of FIG. 3, and for simplicity, only the operation of the upper 4 bits is shown. Figure (a) is a pulse timing chart, (
b) shows the level of charge at node 44. Pulses φPi and φP2 are applied to the gate terminal 41 on the charge injection side.
．． 61, φDI, φD2 are the gate terminals 4 on the extraction side
2.62 respectively.

It is now assumed that the level of the input signal is the level shown at 71 in FIG. 5(b). First, φP1 is applied and a constant charge Q
l is sequentially injected into the node 44. In this example, one injection is set to 1/4 of the full level.

It increases sequentially like 1/4 in tlt and 174 in tx2.
At ts, the level of the signal is exceeded, and the comparator 16 outputs an inverted output. This output is detected and fed back to the controller 18, and φP1 is held at a low level. Next, apply φD1 only once and take out 1/4 of the charge (t=Ha)
. Next, when φP2 is applied sequentially, the gate capacitance becomes CO
/4, the amount of charge carried is Ql/4, and the charge at node 44 is (-'10''>
16 (t=tls) (, 100) (t = , Ha). Since the signal level exceeds the signal level at t=t1s, the output of the comparator 16 is inverted, and the output of is detected and fed back to the controller 18 to hold φP2 at a low level. Thereafter, the levels of lower bits are determined in the same manner. In the first operation, the output of the comparator is inverted at the 3/4 point, so the upper two bits are (1o). In the following behavior (
1+1), so the 3.4th high-order bit of 8 is (01). Therefore, the upper 4 bits are (1001). Thereafter, the lower bits are determined in the same manner and a digital signal is output from the encoder 17.

As described above, the reference voltage generation section of the present invention uses charge transfer elements to generate accurate charges that are not affected by power supply fluctuations, and also provides multiple rows of charge transfer elements to increase speed. By repeating charge injection (maximum 4 times in the above example) in the charge transfer element, the maximum to minimum ratio of the gate poles can be reduced (64:1 in the above example).
, and the corresponding resolution (-8 bits on the bit number)
By using a very small number of charge transfer elements (four rows in the above example), an extremely small device with high resolution and relatively high speed can be realized.

Compared to the conventional successive approximation method that uses only the capacitance ratio (the example was given earlier), the ratio between the maximum and minimum capacitances in the above example only needs to be 1/4; Due to the nonlinearity of gate capacitance, other parts, such as ht-pol
y s i , poly B 1-polySi, etc., but in the present invention, since the charge transfer device only injects a fixed amount of charge, the nonlinearity of the gate of the charge transfer device is not a problem. Therefore, in general, a gate capacitor having a large capacitance per unit area can be used, and a device with a small area can be obtained.

FIG. 6 shows an example of a specific circuit diagram of the configuration shown in FIG. In the figure, 101 is the reference voltage generation section explained in FIGS. 2 to 5, 102 is the comparison section, and 103 is the signal input side. It is coupled to the signal line 104.

Further, 105 is an encoder including an output buffer.

The portion of the solid-state imaging device shown at 103 is schematically shown.

106 is a photodiode, 107 is a vertical readout gate,
A group of gates shown at 108 performs what is called "priming water transfer." 109 is a blooming drain and gate, 110 is a reset gate, and 111 is a source follower serving as a buffer. Solid-state imaging devices that perform priming transfer are described in detail in utility models and patents that have already been filed. (Aoki et al.
4-5100. Ozaki et al. patent application No. 57-39368).

The difference here is that the primed signal charge is not sent to a common output terminal in the charge transfer device, but is instead provided in a sample-hold type for each vertical signal line or at least for several vertical signal lines. It is sent to buffer 111 and compared with a reference voltage.

The signal sent to the comparator in this way is compared with a reference voltage, and when the reference voltage crosses the signal voltage, a high level '1 voltage (or pulse) is output to the signal line 112.

The first part of the encoder is a logic circuit controlled by a shift register 113, and the outputs from the shift register are φPi, φP2°φP3 . In synchronization with the comparison unit 102 outputting the determination to the reference output 112 based on the reference output based on the pulse of φP4, it is sequentially applied in the direction from the gates 114 to 117 at the same period as φP1 to φP4. Therefore, the signal lines 118゜119, 120, 121 are each k (00) (
01) Corresponds to (10) and (11).

For example, in the process of determining the upper two bits, if a high level is output to the signal line 112 when the reference voltage is 3/4 as in the example shown in FIG. is set to high level by gate 124, signal line 123 is set to low level by gate 125, and a (1,0) signal is sent to the output side.

At the same time, since the signal line 121 is fixed to a low level by the gate 126, the signal will no longer be transmitted to the signal line 121 even if the gate 117 is opened next. In this case, since the upper 2 bits are determined, a pulse is applied to the terminal 130, gates 131 and 132 are opened, and the signals 122 and 123 are outputted (held at the output terminals of the sofas 141 and 142.The same applies hereafter). Repeat this cycle to determine the lower output 2 bits at a time, and hold it at the output terminals 143 to 148.
If 52 is made conductive, all bits can be read in parallel.

As described above, the A/D converter according to the present invention shown in FIG. 6 has a simple circuit and a small scale, so it is possible to realize an extremely small device, and it can be formed in one corner of a chip of another functional device.
A revolutionary single-chip multifunctional device can be realized.

Moreover, since it is extremely small, it is easy to form a plurality of them on a part of one chip. In this case, for example, by accessing each gate 152 using a shift register 151 as shown in FIG. 6, the outputs from each A/D conversion device can be taken out sequentially. Here, since the shift registers 113 and 151 can be shared among the A/D converters, the area per each device is effectively further reduced. In this way, the input signals can be processed in parallel,
A multifunctional device that can process high-speed signals with high precision can be easily realized.

In the above explanation, the case where electrons are used as the information source is used, but the case where holes are used can be similarly applied by reversing the pulse, the polarity of the power supply, and the conductivity type of the semiconductor. Further, the encoder shown in FIG. 6 is not limited to this, and a modified version of the encoder or other circuits may be used.

Based on the standard shown in Fig. 3, the pressure generating section has an 8-bit A/D
As an example of a conversion device, we have shown an example in which charge transfer elements are arranged in four columns and charge is injected a maximum of four times in each column, but this is not limited to this example. For each charge transfer device, it is sufficient to perform charge injection up to 2M times. In this case, the maximum and minimum ratio of the storage gate capacitance of the charge transfer device is 2M.
is generally a positive integer, but M is not necessarily an integer. Furthermore, it is not always necessary to make the maximum number of charge injections of each charge transfer element the same. The storage gate capacitance of each charge transfer element may also be combined in different ratios depending on each case. Further, other structures and driving methods of the charge transfer element may be considered, and it goes without saying that the structure and driving method are not limited to those described above.

〔Effect of the invention〕

As explained above, according to the present invention, an accurate reference voltage can be generated at high speed by providing multiple rows of charge transfer elements with different storage gate capacitance values in parallel and injecting charge repeatedly. By using the standard Narita generator that can perform this function, an extremely small A/D converter with high resolution and high conversion speed can be realized, and this can be mounted on a chip on which other functional devices are formed. Te1~
It is possible to realize a small multifunctional device that can constitute one system using several chips.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example of the present invention, and FIG. 2 is a diagram showing a conventional example of the present invention.
3 is a partial detailed circuit diagram of FIG. 2, FIGS. 4 and 5 are explanatory diagrams of operations related to the present invention, and FIG. 6 is a detailed diagram of the present invention. Figure ■ 3 Box 4 Figure 5 Figure 4tLsB in Figure 6

Claims (1)

[Claims] 1. Input signal sample and hold section, reference voltage generation section,
In a device for converting an analog signal into a digital signal, which includes at least a drive section for a reference voltage generation section, a control section for the drive section, a comparison section, and an encoder, the reference voltage generation section sequentially increases or decreases in fixed steps. An analog-to-digital conversion device comprising a plurality of voltage generators that generate voltage, and each voltage generator has a different amount of increment.