JPS59162688A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To heighten sensitivity of detection and enable to drive succeeding output buffer perfectly by making current capacity of a normally on type FET of a differential circuit that constitutes a sense amplifier smaller than current capacity of a normally off type FET by a specified quantity. CONSTITUTION:Current capacity of a normally off type E.FET is made 70N100% that of a normally on type D.FET. However, threshold value voltage of each FET is so controlled that current capacity per unit area of E.FET and D.FET become nearly equal. A differential amplifier 42 is of conventional type. In this circuit which is made a sense amplifier added with level shift circuits 41, 43, output potential V01, V02 is level shifted by -0.74V by diodes 46a, 46b, and V01 becomes -0.04V and V02 becomes 1.04V. D.FET 47a, 47b are connected to diodes 46a, 46b to make the output circuit on, off completely. For input voltage difference, even when the difference is -0.1V, output voltage difference becomes -0.6V, and the sensitivity is -3 times compared with conventional inverter type sense amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a differential amplifier circuit used in a semiconductor integrated circuit.

[Prior art and its problems]

In recent years, field effect transistors made of gallium arsenide crystals (
High-speed integrated circuits (ICs) using Ga'AsFETs are attracting attention. (}aAs ICs include those using normally-on GaAs FETs (hereinafter referred to as D.FETs) and those using normally-off type GaAs F'BTs (hereinafter referred to as E.FETs).
There is one using ET'). The latter has a simpler circuit configuration than the former and is suitable for RC and LSI, and high-speed, high-density memory using this circuit system has also been developed.

A semiconductor memory is composed of several circuit blocks, but the most important circuit that affects performance is a sense amplifier that detects minute signals from memory cells. Silicon crystal (S
i) an insulated gate field effect transistor (MO
Various types of sense amplifier circuits have been proposed for memories using SFETs. On the other hand, regarding the above-mentioned GaAs memory, there are few proposals for sense amplifier circuits, partly because development has just begun. Even though it is a GaAs memory, the basic concept for the sense amplifier circuit is the same. However, since the power supply voltage, signal amplitude, etc. are different from Si memory, the sense circuit used in S1 memory cannot be used as is.

FIG. 1 shows a functional circuit block diagram of a semiconductor memory.

The signals in the memory cell array (12) are called by the signals at the X and Y addresses (lla, 1lb), but the H:q
Assuming that the h-side doubled signal V■H1L□w-side signal is yIT, the sense amplifier circuit detects and amplifies the difference ΔVr (=V■-Vl). Therefore, the number one requirement for the sense amplifier circuit 0 is how small Δ■■ can be detected. Next, the second most important requirement is that the signals ①o and Vo output from the sense amplifier circuit α east can completely drive the output buffer circuit ②.

The sense amplifier circuit α-type usually takes the form of a differential amplifier. G
The same applies to aAs memory, and the one that has been used so far is shown in FIG.

As is clear from FIG. 2, this type of differential amplifier circuit consists of FETs (21a, 21b), E, FET (2
2a), (22b).

(22C). The input/output transfer characteristics of this type of circuit are FET' (21a), (22a
) and (22c), the current capacity is Wa), (
Wb) and (We) vary greatly. However, Wa,
It is assumed that Wb and Wc have the same current capacity per unit. An overview of how the input/output transfer characteristics change will be explained using FIG. In normal sense amplifiers, WA, WB < Wo
In many cases, the problem is WA and WB.
It is a size relationship. When WA<WB, the operating point is similar to that of a normal inverter f3) Trace the point shown by the black circle (curve A) in the figure. Here, ■8 means a common source potential. As is clear from this figure, the input voltage difference △■
When I (=vI-VI) is small, the operating point moves slowly and the output signals are difficult to separate. The fb1 diagram shows this situation. This is a solid line (A). In the case of WA to WB, the output signals are separated immediately even if the input voltage difference is small.

This situation is shown in the case of 8 curves in the +ai diagram.
(1)) This is the dashed line surface in the figure. WA>WB ((a)
(C curve in the figure, 07 curve in the figure (b)) and operates as an amplifier.

In this way, from the viewpoint of sensitivity to input signals, which is the first requirement for a sense amplifier, the case of WA%WB is better, as is clear from the fb1 diagram. However, WA~W
When it is set to B, the low level of the output signal, Vo, increases. Now, set the LOW level potential necessary to drive the output cover sofa circuit that follows the sense amplifier to v7.
Then, in the case of WA-WB, Vb<Vo. For these reasons, with conventional GaAs memory sense amplifiers, WA<WB at the expense of detection sensitivity.
It was common to have an inverter-like configuration.

[Promise of invention]

The present invention has been made to overcome these drawbacks of conventional differential amplifier circuits, and provides a differential amplifier circuit that has high detection sensitivity and is designed to perfectly drive the next output buffer circuit. be.

[Summary of the invention]

The differential amplifier circuit claimed by the present invention is: (1) The laminar flow capacitance value of each FET of the differential circuit constituting the sense amplifier is expressed by the symbol shown in FIG. 2: 0.7WB≦WA
≦WB. ■The output of the differential circuit is equipped with a level shift (level shift) circuit using diodes.
It's something like this.

[Embodiments of the invention]

Hereinafter, the differential amplifier circuit according to the present invention will be explained in detail using specific examples. FIG. 4 shows one specific embodiment. Here, the value shown for each FET K is the gate width/gate length (unit: /J) of the FET.

However, %E, FBT, current capacity per unit area of 1'BT (E, FET, drain saturation current when gate bias is +0, 7V; D, FBT, drain saturation current when gate bias is +O, OV) The saturation current) controls the threshold stress of each FET in almost the same way. The differential amplifier section (421 is of the conventional type, but it is WAzWB. In the circuit as it is, the output voltage V.1 + ■02 becomes as shown in the solid line in Figure 5. However, in this figure, VDn =
This is an example of 2V. H: The output voltage VO1 on the qh side is ~
It was 1.8V, and the Low side was ~0.8V. It can be seen that even if the input voltage difference is small, the outputs are largely separated, producing the effect of wA;WB. However, VO2≧0
．． The potential of 8V is directly applied to DC'F'L (D:rect Coupled FE) of GaAsE-FET configuration.
If it is connected to a T Lop:c) type output circuit, the first stage FET of the output circuit cannot be turned OFF. Therefore, a level shift circuit (4υ) according to the present invention as shown in FIG.
a) (46b) ~074V Rehel Shift Sal, Vol.
becomes ~004V, and voz becomes 1.04V. Note that the above diodes (46a) (46b) K D-FET (4
7a) (47b) are connected. In this way, the output circuit can be completely turned on and off. Moreover, the difference in input voltage is ~0.1. Even at V, the output voltage difference is ~0.6V, which is ~3 times as sensitive as the input voltage difference of ~0.3V to produce the same output voltage difference with a conventional inverter type sense amplifier. .

〔Effect of the invention〕

As described above, according to the present invention, it is possible to completely satisfy the two basic requirements required of a memory sense amplifier as described above. There are two points to be careful about in this circuit.

It is a level shift diode (46a) (46b)
The size WD of the FBT (47a) (47b) connected below is W,,W.

The goal is to make sure that it is no larger than the . This is because when WD is large, the current flowing through the load FgT flows into the level shift side, and the differential amplifier effectively approaches an inverter type, resulting in a decrease in sensitivity. Specifically, WD is 1/3 of WA.
~115 is good.

These problems can be eliminated by using a level shift circuit that does not depend on the size of WD. FIG. 6 shows another example of a sense amplifier belonging to the present invention. The level shift section (41) (43) is composed of a source follower FET and a diode.In this circuit, the load current of the differential amplifier hardly flows through the level shift circuit side pressure.However, in this circuit, the output signal v01' The dynamic resin of VO2' is at least 0.7V or more, which is the minimum voltage necessary to drive the output balance circuit, but VDD must be ~2.5V or more to obtain it.As shown in Figure 4. The access time for a 256-bit GaAs static RAM using a sense amplifier was 3.6 ns.The access time for a RAM using a normal inverter type sense amplifier fabricated on the same chip was 5.2 ns. This also proves the effectiveness of the sense amplifier according to the present invention.

[Brief explanation of the drawing]

Figure 1 is a circuit block diagram of a semiconductor memory, Figure 2 is a diagram showing the general configuration of a differential amplifier, which is the basis of a sense amplifier, and Figure 3 is a diagram showing the operating point for each FET size of the differential amplifier. FIG. 4 is a circuit diagram of the sense amplifier according to the present invention, FIG. 5 is a diagram showing the operating characteristics of FIG. 4, and FIG. 6 is a diagram showing another embodiment according to the present invention. It is a circuit diagram. 41.43 Two-level shift circuit, 42: Differential amplifier section, 46a, 46b: Diode. Agent Patent Attorney Kensuke Chika (and 1 other person) No.
1 Figure height 4Vss

Claims (3)

[Claims] (1) In a differential amplifier circuit in which two normally-off field effect transistors have a common source and each drain is connected to an active load using a normally-on field effect transistor whose source and gate are common, the normally-on field effect 1. A differential amplifier circuit characterized in that the current capacity of the transistor is 70 to 100 times the current capacity of a normally-off field effect transistor. (2) A patented amplifier circuit characterized in that each drain portion of a normally-off field effect transistor is connected to a level shift circuit composed of a normally-on field effect transistor and a Schottky or PN junction diode. (3) The differential amplifier circuit according to claim 1, wherein the normally-on type and normally-off type field effect transistors are made of gallium arsenide.