[go: up one dir, main page]

JPS59160335A - Decision system for convergence of bridged tap equalizer - Google Patents

Decision system for convergence of bridged tap equalizer

Info

Publication number
JPS59160335A
JPS59160335A JP3374383A JP3374383A JPS59160335A JP S59160335 A JPS59160335 A JP S59160335A JP 3374383 A JP3374383 A JP 3374383A JP 3374383 A JP3374383 A JP 3374383A JP S59160335 A JPS59160335 A JP S59160335A
Authority
JP
Japan
Prior art keywords
signal
circuit
convergence
tap coefficient
equalizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3374383A
Other languages
Japanese (ja)
Other versions
JPH0226892B2 (en
Inventor
Kenichiro Hosoda
細田 賢一郎
Shinji Kawaguchi
川口 伸二
Masayuki Ishikawa
正幸 石川
Masaaki Sasagawa
笹川 正明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3374383A priority Critical patent/JPS59160335A/en
Publication of JPS59160335A publication Critical patent/JPS59160335A/en
Publication of JPH0226892B2 publication Critical patent/JPH0226892B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03146Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a recursive structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To obtain resistance to a noise by deciding the convergence of an equalizer by ANDing the repetitive frequency of a tap coefficient with a pattern detection signal. CONSTITUTION:A signal (e.g. AMI code sequence) applied to an input terminal 2-1 is led to an output terminal 2-2 through a correcting signal adding circuit 2-9 and an identifying circuit 2-3, and part of this signal is applied to a pattern detecting circuit 2-5. This pattern detecting circuit 2-5 when detecting specific patterns of 0, + or -1, 0, and 0 sends the pattern detection signal to one input terminal of an AND circuit. The signal from an error polarity detector 2-4, on the other hand, is applied to the other terminal of said AND circuit and ANDed with said pattern detection signal. Consequently, a tap coefficient counter 2-6 counts up or down according to the value of the AND between the error polarity signal (repetitive frequency of tap coefficient) and pattern detection signal to reach convergence.

Description

【発明の詳細な説明】 (技術分野) 本発明は自動等化器の収束判定方式に係り、特に信号に
含まれる波形歪みに対する収束判定が、雑音に強く、確
実に行え、かつ簡単な回路で実現でき、しかも波形歪み
としてメタリック線路の分岐線路(ブリッジド タップ
線路)のパルス反射にもとづく波形歪の正確でじん速な
等化が可能なブリッジドタップ等化器の収束判定方式に
関する。
[Detailed Description of the Invention] (Technical Field) The present invention relates to a convergence determination method for an automatic equalizer, and in particular, convergence determination for waveform distortion contained in a signal is resistant to noise, can be performed reliably, and is performed using a simple circuit. The present invention relates to a convergence determination method for a bridged tap equalizer that can be realized and that can accurately and quickly equalize waveform distortion based on pulse reflection of a branch line (bridged tap line) of a metallic line as a waveform distortion.

(従来技術) 第1図は、信号に含まれる歪の自動波形等化器の従来列
のブロック図である。第1図は、信号の入出力端子1−
1,1−2、補市波形加算器1− 、?、識別回路1−
4、エラー極性判定回路1−5、時間Tの遅延回路1−
6、タップ係数更新回路1−7、D/A変換器1−8、
低域フィルタl−9よ多構成される。
(Prior Art) FIG. 1 is a block diagram of a conventional array of automatic waveform equalizers for distortion contained in a signal. Figure 1 shows the signal input/output terminal 1-
1, 1-2, auxiliary waveform adder 1-, ? , identification circuit 1-
4. Error polarity determination circuit 1-5, time T delay circuit 1-
6, tap coefficient update circuit 1-7, D/A converter 1-8,
It is composed of multiple low-pass filters l-9.

第1図の系において、等化器の収東時には、自動制御を
受けたタップ係数の値が一定値を中心として増減をくシ
返すことを利用して、このタッグ係数の増減を行ってい
た。しかし、タップ係数の増減のくシ返しは、等止器の
発散状態においても起き、また雑音によっても生ずるこ
とが知られ等止器が確実に収束しだか否かの保証が得ら
れない欠点を有していた。
In the system shown in Figure 1, when the equalizer adjusts, the tag coefficient is increased or decreased by utilizing the fact that the value of the automatically controlled tap coefficient increases or decreases around a constant value. . However, it is known that the repeating increase/decrease of the tap coefficient occurs even when the isolator is in a diverging state, and is also caused by noise, so it has the disadvantage that it cannot be guaranteed whether the isolator has converged or not. had.

(発明の目的) 本発明の目的は従来雑音又は回路自体の不安定性によっ
て惹起された収束判定の誤1りを除去することの出来る
収束判定方式を提供するにある。
(Object of the Invention) An object of the present invention is to provide a convergence judgment method capable of eliminating convergence judgment errors caused by conventional noise or instability of the circuit itself.

(発明の概要) この発明では上記目的を達成するだめに、あらかじめ定
めた特定パターンが検出された時のみタップ係数制御を
行うようにすることによって、り7プ係数のくシ返し回
数と・9タ一ン検出信号との論理積として等止器の収束
判定を行うようにしたことを特徴としている。以下実′
施例に基づいて詳細に説明する。
(Summary of the Invention) In order to achieve the above object, the present invention performs tap coefficient control only when a predetermined specific pattern is detected. It is characterized in that the convergence determination of the isolator is performed as a logical product with the tangent detection signal. Actual below
This will be explained in detail based on an example.

(発明の実施列) 第2図は、本発明の一つの実施列を示すブロック図であ
って、帰還ディジタル フィルタの次数が2次即ち2タ
ツプの例である。入出tJ端子2−1゜2−2、識別器
2−3、エラー極性検出器2−4、パターン検出器2−
5、係数カウンタ2−6、D/A変換器2−7、ローノ
やス フィルタ2−8、補正信号加算回路2−9よ勺構
成されている。
(Embodiment of the Invention) FIG. 2 is a block diagram showing one embodiment of the present invention, and is an example in which the order of the feedback digital filter is 2nd order, that is, 2 taps. Input/output tJ terminal 2-1゜2-2, discriminator 2-3, error polarity detector 2-4, pattern detector 2-
5, a coefficient counter 2-6, a D/A converter 2-7, a filter 2-8, and a correction signal addition circuit 2-9.

その動作を、AMI符号列(0,±1.0.0)に歪波
形成分が加った信号を、入力信号の例として説明する。
The operation will be explained using a signal obtained by adding a distorted waveform component to the AMI code string (0, ±1.0.0) as an example of an input signal.

第3図(a)は、歪波形成分を含むAMI符号列(o、
t、o、o)の例を示す。第3図(a)において、横軸
3−1は、時間の進みを示す。タテ軸3−2は、波形の
振幅、3−3は歪を含んだ入力波形、3−4は識別レベ
ルを示す。時間軸3−1上の−T、0.T、2T、3T
は識別回路2−3における識別タイミング時間である。
FIG. 3(a) shows an AMI code string (o,
Examples of t, o, o) are shown below. In FIG. 3(a), the horizontal axis 3-1 indicates progress of time. The vertical axis 3-2 shows the amplitude of the waveform, 3-3 shows the input waveform including distortion, and 3-4 shows the discrimination level. -T on time axis 3-1, 0. T, 2T, 3T
is the identification timing time in the identification circuit 2-3.

識別回路2−3は、タイミング時間において、第3図(
b)に示した様に(0,+1.+1.O)と判定し、時
間T毎に順番にシフトし、時間Tの遅延器2−10.2
−11とパターン検出器2−5に出力する。パターン検
出器2−5は、特定・母ターン(本例では、0.±1,
0゜0)の検出と、バイポーラ・バイオレーション則に
違反する信号(本列では、0.+1.+1,0と0、−
1.−1.0とO、+1 、 O、+1と0.−1.0
゜−1)は、訂正し、特定・ゼターン検出として、・ぐ
ターン検出1言号を発生する。
The identification circuit 2-3 is configured to operate as shown in FIG.
As shown in b), it is determined as (0, +1.+1.O) and shifted in order at each time T, and the delay device 2-10.2 of time T
-11 and is output to the pattern detector 2-5. The pattern detector 2-5 detects a specific/main turn (in this example, 0.±1,
0°0) and a signal that violates the bipolar violation law (in this column, 0.+1.+1,0 and 0,-
1. -1.0 and O, +1, O, +1 and 0. -1.0
゜-1) is corrected and generates one word for the specific turn detection.

一方、エラー極性検出器2−5において、タイミング時
間における入力信号の極性を検出する。
On the other hand, the error polarity detector 2-5 detects the polarity of the input signal at the timing time.

第3図(c)は、エラー極性検出器2−4の出力である
FIG. 3(c) shows the output of the error polarity detector 2-4.

iPターン検出信号は、ディジタル フィルタの各タッ
プに出力され、エラー極性信号と論理積を行う。タップ
係数カウンター2−6は、エラー極性信号と・ぐターン
検出信号との論理積の結果に応じて、カウント アップ
又はカウント ダウンする。タップ係数カウンター2−
6の精度は、D/A変換器2−7の量子化ビット数と同
一に選ばれる。
The iP turn detection signal is output to each tap of the digital filter and ANDed with the error polarity signal. The tap coefficient counter 2-6 counts up or down depending on the result of ANDing the error polarity signal and the turn detection signal. Tap coefficient counter 2-
The precision of 6 is selected to be the same as the number of quantization bits of the D/A converter 2-7.

補正信号は、時間Tの遅延器2−10.2−11の出力
と、各タップ係数カウンタ2−6の出力との論理積を加
算器2−12で加算し、い変換器2−7にてアナログ信
号に変換され、ローパスフィルタ2−8で帯域制限され
て得られる。帯域制限された補正信号は、加算器2−9
で歪を含んだ入力信号と加算される。
The correction signal is obtained by adding the logical product of the output of the delay device 2-10. The signal is converted into an analog signal by a low-pass filter 2-8, and the signal is band-limited by a low-pass filter 2-8. The band-limited correction signal is sent to the adder 2-9.
is added to the input signal containing distortion.

以上説明した系の7ミユレーシヨンにより得れたタップ
係数の収束過程を第4図に示す。第4図において、4−
1は、■タップ目のタッグ係数、4−2は2タツプ目の
タップ係数である。横軸4−3は、タップ係数の更新回
数、タテ軸4−4は係数値、破線4−5は、等止器のタ
ップ係数が収束状態に入る基点である。本例では、約3
5回のタップ係数更新によって、収束状態に移行してい
る。等止器が収束状態に入ると各タップ係数は、一定値
で増減をくり返えす。又、この段階では、入力信号の歪
波成分は、はとんど補正され・4タ一ン検出回路2−5
は、確実に特定・母ターンを検出できる。タップ係数の
収束判定は、タップ係数の収束過程における一定値の増
減をカウントし、予め定めた値に達した時係数収束信号
を発生することによって行う。したがって等止器の収束
判定を、フラジ係数収束信号と、ノソターン検出信号の
両方を考慮して行うことによシ、確実に等止器の収束状
態を判定することができる。
FIG. 4 shows the convergence process of the tap coefficients obtained by seven simulations of the system described above. In Figure 4, 4-
1 is the tag coefficient of the ■th tap, and 4-2 is the tap coefficient of the second tap. The horizontal axis 4-3 is the number of updates of the tap coefficients, the vertical axis 4-4 is the coefficient value, and the broken line 4-5 is the base point at which the tap coefficients of the isolator enter a convergence state. In this example, approximately 3
By updating the tap coefficients five times, a transition is made to the convergence state. When the equalizer enters the convergence state, each tap coefficient repeats increases and decreases at a constant value. Also, at this stage, the distorted wave components of the input signal are mostly corrected.
can reliably detect the specific/mother turn. Convergence determination of the tap coefficients is performed by counting increases and decreases of a constant value in the convergence process of the tap coefficients, and generating a coefficient convergence signal when a predetermined value is reached. Therefore, by determining the convergence of the equalizer by considering both the Flaj coefficient convergence signal and the nosoturn detection signal, it is possible to reliably determine the convergence state of the equalizer.

なお、以上の記述においては、自動等止器の制御動作が
、系の動作の初期段階すなわち、トレーニング段階にあ
る場合について記述した。一方、トレーニング段階が終
了し、系が正常動作に移行した場合においても、さらに
等止器の状態を変更する必要が生ずる場合がある。これ
は、系が経時的に特性変動する場合である。トレーニン
グ状態においては、等化動作は可及的速かに行われる必
要があるのに対して、正常動作時においては、むしろ動
作が緩和して行われることが求められる。
In addition, in the above description, the case where the control operation of the automatic isolator is in the initial stage of system operation, that is, in the training stage has been described. On the other hand, even when the training phase has ended and the system has returned to normal operation, it may be necessary to further change the state of the isolator. This is the case when the characteristics of the system change over time. In the training state, the equalization operation needs to be performed as quickly as possible, whereas during normal operation, the equalization operation is required to be performed more slowly.

これを実現する方法として、信号中に確率的に含りる特
定・ぐターンを検出し、かつ、その回数が予じめ設定し
た回数に達した時のみ、前記タップ係数の更新を行うこ
とによシ達成できる。これは、タップ係数更新のガード
 タイムを設定することにより行なう。
As a method to achieve this, the tap coefficients are updated only when a specific turn that is stochastically included in the signal is detected and the number of times it is detected reaches a preset number of times. You can achieve it. This is done by setting a guard time for updating the tap coefficients.

次に、信号にノイズが含れて、等化動作が見かけ」二完
了する場合がある。これに対して、予じめ設定泗れた直
に、前記カウンタのアップ・ダウンのくシ返し回数が達
する前に、停止した場合には、その時点までのカウント
数を零にリセットすることによシ雑音による誤動作を軽
減することができる。
Next, the signal may contain noise, causing the equalization operation to appear to be completed only once. On the other hand, if the counter stops before reaching the number of up and down cycles that have been set in advance, the count up to that point will be reset to zero. Malfunctions caused by noise can be reduced.

(発明の効果) 以上説明したように、この発明では、タップ係数の収束
信号と、・やターン検出信号との論理積によって、等止
器の収束判定を行うだめ、雑音にも強く、確実に等止器
の収束判定を行うことができる。
(Effects of the Invention) As explained above, in the present invention, the convergence determination of the equalizer is performed by the AND of the convergence signal of the tap coefficient and the turn detection signal, which is resistant to noise and reliable. It is possible to determine the convergence of the equistopper.

以上の説明においては、簡単のため特定パターンとして
AMI系列系列上2±1.0を用いた場合について記述
したが、本発明は他の任意の符号形式、符号系列に対し
ても適用される。さらに信号に含捷れる歪成分が分岐線
路(ブリッジドタップ線路)に起因する場合以外につい
ても適用されることは明らかである。
In the above description, for simplicity, a case has been described in which 2±1.0 on the AMI sequence is used as the specific pattern, but the present invention is also applicable to any other code format or code sequence. Furthermore, it is clear that the present invention is also applicable to cases where the distortion component included in the signal is not caused by a branch line (bridged tap line).

本発明は、ディノタル加入者線伝送において、反射に基
づく・々ルス伝送歪を等化する波形歪の自動等化器の収
束判定に非常に有効でアシ、又、特定・ぐターンにより
等止器を収束させる方式には、広く利用することができ
るものである。
The present invention is very effective in determining the convergence of an automatic equalizer for waveform distortion that equalizes the transmission distortion caused by reflection in Dinotal subscriber line transmission. The method for converging can be widely used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の判定帰還形自動等化器の一般例を示すブ
ロック図、第2図は本発明の一実施例を示すブロック図
、第3図は第2図に示した回路における動作の説明図、
第4図は第2図に示した回路のシュミレーションによっ
て得たタ+プ係数のl収束過程を示す説明図である。 2−1.2−2・・・入出力端子、2−3・・・識別回
路、2−4・・・エラー極性判定回路、2−5・・・パ
ターン検出器、2−6・・・タップ係数更新カウンタ、
2−7・・・色変換器、2−8・・ローノRスフィルタ
、3−1・・・時間軸、3−2・・・波形振幅、3−3
・・・入力波形、3−4・・・m 別レベル、4−1.
4−2・・タップ係数、4−3 係数更新回数。 l 宇にの着生 昭和58年 q、!l  豹  願第033743  
号2 発明の名称 シリノットタップ等止器の収束判定方式:う、補止をす
る者 事件との関係      特 許 出 願 人イJ、 
所(〒] +) 5 )   東京都港区虎ノ門l]−
目″番12号住 所(〒105)  東京都港区虎ノ門
1丁目7番12号5 捕市の7−J象 図面中「第1図
」及び「第2図」(j 谷011−の内容 別紙のとお
り口面「′硲10..l隨ひ「箔2目1.癲征する 第1図
FIG. 1 is a block diagram showing a general example of a conventional decision feedback type automatic equalizer, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 shows the operation of the circuit shown in FIG. Explanatory diagram,
FIG. 4 is an explanatory diagram showing the convergence process of tap coefficients obtained by simulation of the circuit shown in FIG. 2. 2-1.2-2... Input/output terminal, 2-3... Identification circuit, 2-4... Error polarity determination circuit, 2-5... Pattern detector, 2-6... tap coefficient update counter,
2-7... Color converter, 2-8... Ronos filter, 3-1... Time axis, 3-2... Waveform amplitude, 3-3
...Input waveform, 3-4...m different level, 4-1.
4-2...Tap coefficient, 4-3 Coefficient update count. l Epiphytic growth of sea urchins in 1982 q,! l Leopard Application No. 033743
No. 2 Name of the invention Convergence judgment method for Sirinot tap stopper: Relationship with the supplementary case Patent application Person I J.
Location (〒] +) 5) Toranomon l]-, Minato-ku, Tokyo
No. 12 Address (〒105) 1-7-12-5 Toranomon, Minato-ku, Tokyo 7-J Elephant in Toriichi "Figure 1" and "Figure 2" in the drawing (contents of j Valley 011-) As shown in the attached sheet, the mouth surface "'硲10..l隨hi" 2 pieces of foil 1. Figure 1 of the attack.

Claims (1)

【特許請求の範囲】[Claims] ディノタル信号の識別回路、補正信号発生のだめのディ
ジタルフィルタ、および、・該ディジタルフィルタのタ
ッグ係数を制御するだめの制御回路とよシ成る判定帰還
型自動等化器の収束判定方式あらかじめ定められた特定
パターンの検出回路と特定・ぐターンが検出された時に
のみ前記タップ係数制御を行う制御回路とを有し、該タ
ップ係数制御1回路が、アップ ダウン カウンタとフ
リップ フリップ回路で構成され、該カウンタのアラ、
 プ・ダウンの〈υ返し回数が設定値に達し、かつ前記
特定パターン検出回路が出力していることの2条件を満
たした時等化器が収束したものと判定し、かつ判定出力
を発生させることを特徴とするブリ7ノドタツプ等化器
の収束判定方式。
A convergence determination method for a decision feedback automatic equalizer consisting of a digital signal identification circuit, a digital filter for generating a correction signal, and a control circuit for controlling tag coefficients of the digital filter. It has a pattern detection circuit and a control circuit that performs the tap coefficient control only when a specific pattern is detected, and the tap coefficient control circuit 1 is composed of an up/down counter and a flip/flip circuit, Alas,
When two conditions are satisfied: the number of <υ returns of pull-down reaches a set value and the specific pattern detection circuit is outputting, it is determined that the equalizer has converged, and a determination output is generated. A method for determining convergence of a 7-nod tap equalizer.
JP3374383A 1983-03-03 1983-03-03 Decision system for convergence of bridged tap equalizer Granted JPS59160335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3374383A JPS59160335A (en) 1983-03-03 1983-03-03 Decision system for convergence of bridged tap equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3374383A JPS59160335A (en) 1983-03-03 1983-03-03 Decision system for convergence of bridged tap equalizer

Publications (2)

Publication Number Publication Date
JPS59160335A true JPS59160335A (en) 1984-09-11
JPH0226892B2 JPH0226892B2 (en) 1990-06-13

Family

ID=12394889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3374383A Granted JPS59160335A (en) 1983-03-03 1983-03-03 Decision system for convergence of bridged tap equalizer

Country Status (1)

Country Link
JP (1) JPS59160335A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0216183A2 (en) * 1985-08-28 1987-04-01 Nec Corporation Decision feedback equalizer with a pattern detector

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197927A (en) * 1982-05-14 1983-11-17 Fujitsu Ltd System for discriminating completion of automatic equalization

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197927A (en) * 1982-05-14 1983-11-17 Fujitsu Ltd System for discriminating completion of automatic equalization

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0216183A2 (en) * 1985-08-28 1987-04-01 Nec Corporation Decision feedback equalizer with a pattern detector

Also Published As

Publication number Publication date
JPH0226892B2 (en) 1990-06-13

Similar Documents

Publication Publication Date Title
US3508153A (en) Automatic equalizer for partial-response data transmission systems
US3633170A (en) Digital filter and threshold circuit
US4118686A (en) Error correction for signals employing the modified duobinary code
CA2002585C (en) Demodulator with composite transversal equalizer and eye detection clock synchronizer
JPH08511665A (en) Judgment return equalizer
JPH09326729A (en) Subscriber line termination circuit
JPS59160335A (en) Decision system for convergence of bridged tap equalizer
CA1225704A (en) Dynamic digital equalizer
US7170930B2 (en) Receiver
US3553606A (en) System for providing adjusting signals to a transversal filter equalizer
US5105440A (en) Method and apparatus for adaptive equalization of pulse signals
US4041418A (en) Equalizer for partial response signals
FI67643C (en) FOERFARANDE FOER FASSYNKRONISERING I ETT SYNKRONT DATATRANSMISSIONSSYSTEM OCH ANORDNING FOER UTFOERANDE AV FOERFARANDET
CA1222291A (en) Transmission response measurements
JPH0330528A (en) Equalizer and performance evaluating method for the same
JP2893683B2 (en) How to design a filter
JPS63177363A (en) Waveform equalizing circuit
JPH01314009A (en) Transversal equalizer control system
JPH0129877Y2 (en)
JPH022334B2 (en)
JPS631781B2 (en)
JPH05291879A (en) Automatic equalizer circuit
JPH08181638A (en) Equalizer and its performance evaluation method
JPS6277723A (en) Reception training system for ping-pong transmission equipment
JPH05227226A (en) Digital signal transmission system