JPS59158516A - Manufacture of electrode and wiring - Google Patents
Manufacture of electrode and wiringInfo
- Publication number
- JPS59158516A JPS59158516A JP3071883A JP3071883A JPS59158516A JP S59158516 A JPS59158516 A JP S59158516A JP 3071883 A JP3071883 A JP 3071883A JP 3071883 A JP3071883 A JP 3071883A JP S59158516 A JPS59158516 A JP S59158516A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- deposited
- tungsten
- wiring
- vapor deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 27
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000010937 tungsten Substances 0.000 claims abstract description 22
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 11
- 229910052750 molybdenum Inorganic materials 0.000 claims description 11
- 239000011733 molybdenum Substances 0.000 claims description 11
- 150000002739 metals Chemical class 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000003340 mental effect Effects 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- 229910052698 phosphorus Inorganic materials 0.000 claims 2
- 239000011574 phosphorus Substances 0.000 claims 2
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000010894 electron beam technology Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は絶縁膜上の選択的に所定の位置に金属を堆積す
る化学気相成長法に係シ、特に１ミクロメートルあるい
はそれ以下の微細配線幅全必要とする高集積シリコン半
導体装置に好適な電極、配線の製造方法に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a chemical vapor deposition method for selectively depositing metal at predetermined positions on an insulating film, and particularly relates to a fine interconnection of 1 micrometer or less. The present invention relates to a method for manufacturing electrodes and wiring suitable for highly integrated silicon semiconductor devices that require full width.
金属−酸化物一半礫体（ＭＯＳ）型シリコン半導体装置
の高集積、高速化に伴い、従来用いられてきた多結晶シ
リコンゲート電極、配線はタングステンやモリブデン等
の高融点金属電極、配線に置きかわりつつある。しかし
ながら、これらの金属をハロゲン化物ガス中でのグラズ
マあるいは反応性スパックエツチングを行なうとサイド
エッチングのため、エツチングマスク用のレジスト線幅
より０．３〜０４ミクロンメートル上記金頃配線が細り
、１ミクロンメートルあるいはそれ以下の電極配線が形
成が難かしいという欠点があった。With the increasing integration and speed of metal-oxide monolithic (MOS) type silicon semiconductor devices, the conventionally used polycrystalline silicon gate electrodes and wiring are being replaced with high-melting point metal electrodes and wiring such as tungsten and molybdenum. It's coming. However, when these metals are subjected to glazma or reactive spack etching in a halide gas, side etching occurs, and the metal wiring becomes thinner by 0.3 to 04 micrometers than the resist line width for the etching mask, resulting in a width of 1 micrometer. There was a drawback that it was difficult to form electrode wiring of meters or less.
また、微細配線形成技術にはリフトオフ法がある。周知
のようにこの方法にはりスト１フ月の耐熱性が悪いため
、高温で金属を形成、できず、良質な金属膜が得られな
い。また約１ミクロン以下の線幅の配線を形成する場合
、リフトオフ材の間隙への金属の堆積が難かしい等の欠
点があった。Further, there is a lift-off method as a technique for forming fine wiring. As is well known, this method has poor heat resistance during the first month of the process, so metal cannot be formed at high temperatures and a high quality metal film cannot be obtained. Furthermore, when forming interconnections with a line width of about 1 micron or less, there are drawbacks such as difficulty in depositing metal in gaps in the lift-off material.
本発明の目的は、ドライエツチング法やリフトオフ法で
難かしかった約１ミクロン以下の幅を有する微細電極、
配線を可能にする製造方法を提供することにある。The purpose of the present invention is to create a fine electrode with a width of about 1 micron or less, which has been difficult with dry etching methods and lift-off methods.
The object of the present invention is to provide a manufacturing method that enables wiring.
上記目的全達成するための本発明の構成は、基板に所定
のパターンで金属の被着を行なう工程と、上記形成され
た領域上に所定の条件で化学気相成長を行なって上記パ
ターンの金属層全堆積して電極配線を形成することにあ
る。The structure of the present invention for achieving all of the above objects includes a step of depositing metal on a substrate in a predetermined pattern, and performing chemical vapor deposition on the formed region under predetermined conditions to form a metal layer in the pattern. The purpose is to deposit all layers to form electrode wiring.
上記金属の破着形成工程としては、イオン打込み法、蒸
着法、スパッタ法が適用される。中でも、イオン打込み
が（傘めて良好であった。上記金属の被着（で便わｆる
金属としてはＡ７．Ｗ、’ＭＯ。An ion implantation method, a vapor deposition method, and a sputtering method are applied to the metal fracture formation process. Among them, the ion implantation was generally good.The metals that were useful for the above metal deposition were A7.W and 'MO.
Ｔａ、 Ｔ；、及びＳｌとすることが肝要である。It is important to set Ta, T; and Sl.
捷だ、化学気相に使われる金属としてばＷ又はへ４０と
することが肝要である。It is important that the metal used in the chemical vapor phase be W or H40.
本発明は、上述の様に化学気相成長法によりタングステ
ンあるいはモリブデンをシリコン酸化膜上に堆積させず
、シリコン基板上にだけ選択的に堆積できる条件を見つ
けたことに基ずくものである。またシリコン基板のかわ
りにア刀・ミニラム。The present invention is based on the discovery of conditions that allow tungsten or molybdenum to be deposited selectively only on a silicon substrate without depositing tungsten or molybdenum on a silicon oxide film by chemical vapor deposition as described above. Also, instead of a silicon substrate, a sword/miniram is used.
タングステン、モリブデン、メンタルあるいはチタン上
Ｖこも選択的にタングステンまたはモリブデンを堆積で
さることが明らかとなった。次にシリコン酸化膜ニシリ
コン、ア兎ミニウムおよびタングステン全イオン打込し
た後、化学気相成長法によりモリブデンあるいはタング
ステンを被着させた結果、イオン打込領域だけにこれら
の金属が堆積できることがわかった。以下、実施例を用
いて訂玉述する。It has become clear that tungsten or molybdenum can be selectively deposited on tungsten, molybdenum, metal or titanium. Next, after implanting all ions of silicon oxide film, silicon, aluminum, and tungsten, molybdenum or tungsten was deposited by chemical vapor deposition, and it was found that these metals could be deposited only in the ion implanted region. . Hereinafter, a detailed explanation will be given using examples.
実施例１； 以下、本発明の一実施例を第１図により説明する。 Example 1; An embodiment of the present invention will be described below with reference to FIG.
シリコン基板１上に形成した酸化膜２上に坏ガ型の電子
線レジストである例えば６Ｍ −ＣＭ Ｓ（クロロメチ
ル化ポリスチレン）３を用い電子ビームｖｃｘ ｐ露光
し、レジスト線幅０．３ミ外ロンメータ、レジスト線間
隔０．３ミクロンメートルのストライブ状パターンを形
成した。続いて遠紫外線を全面に照射した後、上記レジ
スタバター／をマスクとし、タングステン４を試料にイ
オン打込した。イオン打込に際し、打込による試料の外
温を防ぐため、試料台を水冷しかつ回転させながら打込
んだ。打込エネルギは５０から１５０ＫｅＶで打込量は
Ｉ Ｘ １０” ｃｍ−”からＩ Ｘ １０” ｃｍ−
”とした。An oxide film 2 formed on a silicon substrate 1 is exposed to electron beam VCXP using a molded electron beam resist such as 6M-CMS (chloromethylated polystyrene) 3, and the resist line width is 0.3 mm. A striped pattern with a resist line spacing of 0.3 micrometers was formed using a ronmeter. Subsequently, after irradiating the entire surface with deep ultraviolet rays, tungsten 4 was ion-implanted into the sample using the resistor butter as a mask. During ion implantation, the sample stage was cooled with water and was rotated to prevent the sample from being exposed to external temperatures due to implantation. The implant energy is 50 to 150 KeV and the implant amount is I X 10"cm-" to I X 10" cm-
”.
次に打込マスク用レジストを除去後、ホット・ウオール
型の減圧の化学気相成長装置でタングステンを堆積５さ
せた。Next, after removing the implant mask resist, tungsten was deposited 5 using a hot wall type reduced pressure chemical vapor deposition apparatus.
その条件は試料温度４５０ＣでＷ Ｆ ａ とＪ−Ｉ
２の全圧１．３ Ｘ ＩＱ２ｐ ａとし、その時の８２
分圧は１．３Ｐａとし、／で二。The conditions are sample temperature 450C, W Fa and J-I
The total pressure of 2 is 1.3 x IQ2p a, and then 82
Partial pressure is 1.3 Pa, / is 2.
この条件でタングステン全０．２ミクロンメートル堆積
した結果を走査型電子顕微鏡で観察した結果、線１！８
０．４ミクロンメートルのタングステン配線が形成でき
ていることが確認できた。また、タングステンのイオン
打込のかわりに、シリコン。As a result of observing the result of depositing a total of 0.2 micrometers of tungsten under these conditions with a scanning electron microscope, the line 1!8
It was confirmed that 0.4 micrometer tungsten wiring was formed. Also, instead of tungsten ion implantation, silicon.
アルミニウム、モリブデン、メンタルおよびチタンの打
込みも同様に適用できた。これらのイオン打込みののち
、タングステンを選択的に堆積した結果、０３〜０６５
ミクロンの配線が形成できンヒ。Aluminum, molybdenum, mental and titanium implants were equally applicable. After these ion implantations, tungsten was selectively deposited, resulting in 03-065
Micron wiring can be formed.
これらの打込猷属のうち、チタンの場合は他の金属より
化学気相成長法によるタングステンの選択成長に時間が
掛ったが、同様に良質な金属配線が１ｈられた。Among these implantable metals, in the case of titanium, it took longer to selectively grow tungsten by chemical vapor deposition than other metals, but similarly high-quality metal wiring was produced for 1 hour.
実施例２；
本発明の他の実Ｘ例として、Ｍ、、０８トランジスタ全
図２にシｊ（す。Embodiment 2: As another practical example of the present invention, an M, 08 transistor is shown in FIG.
１０Ω・確のＰ型（１００）基板１に熱酸化法により素
子間分離用の５００ｎｍの厚い酸化膜６と、膜厚２Ｑ
ｎｍの薄いゲート酸化膜７を形成した。続いてトランジ
スタのしさい電圧制御のため、イオン打込法によりボロ
ンをＩ Ｘ １０” ／ｃｍ２打込んだ。次にスパッタ
法によシ膜厚ｌＱｎｍのシリコン８を堆積し、前述の実
施例１と同様の方法でレジスＩｆゲート電極形状に形成
し、続いてＣＦ４＋４％０２ガスを用いたプラズマエツ
チング装置゛でレジスト全マスクとして先に堆積した薄
いシリコン８をエツチングした。この後レジスト全除去
し、実施例１と同一の条件でタングステン５を薄いシリ
コン上Ｑて選択的に０．３ミクロンメータの厚さに堆積
した。次にソース、ドレイン９形成のためのひ素を６０
ＫｅＶで５． Ｘ １５ ” ／ｃｍ２イオン打込みし
た。その後、通常の方法で層間絶縁膜用りん硅酸ガラス
１０、アルミニウム電極配線１１゜素子保護用絶縁膜１
２を形成し、ＭＯＳ）シ／ジスタｆｆ：ｒ「成した。こ
のＭＯＳトランジスタの設計チャンイ、ル長は０．５ミ
クロンメータであるが形成できたタングステンのゲート
電極幅は０．６５ミクロンメークであった。ＭＯＳトラ
ンジスタは正常動作を示し、そのしきい電圧は０．２
Ｖであった。A thick oxide film 6 of 500 nm for isolation between elements and a film thickness of 2Q are formed on a P-type (100) substrate 1 of 10 Ω by thermal oxidation.
A gate oxide film 7 as thin as 7 nm was formed. Next, in order to control the voltage of the transistor, boron was implanted at I x 10"/cm2 by an ion implantation method. Next, silicon 8 was deposited to a thickness of 1Q nm by a sputtering method. A resist If gate electrode shape was formed in the same manner as above, and then the thin silicon 8 deposited earlier was etched as a mask for the entire resist using a plasma etching device using CF4+4%02 gas.After that, the entire resist was removed. Tungsten 5 was selectively deposited on thin silicon to a thickness of 0.3 μm under the same conditions as in Example 1. Next, 60 μm of arsenic was deposited to form the source and drain 9.
5 at KeV. X 15"/cm2 ions were implanted. After that, phosphosilicate glass 10 for interlayer insulating film, aluminum electrode wiring 11° and insulating film 1 for device protection were formed using the usual method.
The design length of this MOS transistor was 0.5 micrometers, but the width of the tungsten gate electrode was 0.65 micrometers. The MOS transistor showed normal operation, and its threshold voltage was 0.2.
It was V.
以上詳述した様に、本発明によれば、１ミクロンメート
ル以下の微細配線を精度良く形成できるので、超高集積
半導体装置の高密度化を容易にする効果がある。これは
本発明の金属をイオン打込する方法では電極、配線用金
属の加工工程が省略でき、また、薄い金属をタングステ
ンやモリブデンの選択成長の核として敷く方法では下地
金属が極めて薄いためこれらの金属のドライエツチング
時のナイドエツチングをほとんど無くすることができる
ためである。As described in detail above, according to the present invention, fine interconnections of 1 micrometer or less can be formed with high accuracy, which has the effect of facilitating high-density ultra-highly integrated semiconductor devices. This is because the method of ion-implanting metal according to the present invention can omit the process of processing metal for electrodes and wiring, and the method of laying thin metal as a nucleus for selective growth of tungsten or molybdenum requires extremely thin base metal. This is because it is possible to almost eliminate nide etching during dry etching of metal.
第１図は本発明の一実施例としての微細配線形成工程図
、第２図は本発明の他の実施例としてのＭｏｓトランジ
スタ形成工程図である。
１・・・シリコン基板、２・・・酸化膜、３・・・レジ
スト、４・・・イオン打込された金属、５・・・選択成
長した金属、６・・・素子間分離用酸化膜、７・・・ゲ
ート酸化膜、８・・・薄い金属膜、９・・・ソース、ド
レイン、１ｏ・・・層間絶縁膜、１１．１２・・・電極
、配線、１２・・・素子保護用絶縁膜。
Ｆ
第 １ 図
雨 ２ 図
；５FIG. 1 is a process diagram for forming fine wiring as one embodiment of the present invention, and FIG. 2 is a process diagram for forming a Mos transistor as another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film, 3... Resist, 4... Ion-implanted metal, 5... Selectively grown metal, 6... Oxide film for isolation between elements , 7... Gate oxide film, 8... Thin metal film, 9... Source, drain, 1o... Interlayer insulating film, 11.12... Electrode, wiring, 12... Element protection Insulating film. F Figure 1 Rain 2 Figure; 5
Claims (1)
よびスパッタ法の金属被着方法群からなる少く共１種を
用いて金属を被着する工程、その後、化学気相成長法に
より、上記基板上のうち金属全被着せしめた領域のみに
金属を堆積し電極配線を形成することを％徴とする電極
配線の製造方法。 ２、特許請求の範囲第１項において、上記基板として、
シリコン酸化物あるいはりんおよび沓ロンを含有するシ
リコン酸化物もしくはシリコン輩化物とし、打込金属を
アルミニウム、タングステン、モリブデン、メンタルお
よびチタンなどの金属あるいはシリコンとし、堆積金属
をモリブデンあるいはタングステンとすることを特徴と
する電極・配線の製造方法。 ３、特許請求の範囲第１項において、上記金属被着法に
！る金属薄膜の厚さを２〜５Ｑｎｍの厚さに堆積し、続
いて所定の形状に加工後、化学気相成長法により、これ
らの金属上にのみ選択的にモリブデンあるいはタングス
テンを堆積し、電極配線を形成することｆ：％徴とする
電極配線の製造方法。[Scope of Claims] 1. A step of depositing metal on a predetermined position on a substrate using at least one of the metal deposition methods group consisting of ion implantation vapor deposition method and sputtering method, and then, A method for producing electrode wiring, the method comprising depositing metal only on the area on which metal is completely deposited on the substrate by chemical vapor deposition to form electrode wiring. 2. In claim 1, as the substrate,
The method is to use silicon oxide or a silicon oxide or silicon compound containing phosphorus and phosphorus, to use metals such as aluminum, tungsten, molybdenum, mental and titanium, or silicon as the implanted metal, and to use molybdenum or tungsten as the deposited metal. Characteristic electrode/wiring manufacturing method. 3. In claim 1, the above-mentioned metal deposition method! A thin metal film is deposited to a thickness of 2 to 5 Qnm, and after processing into a predetermined shape, molybdenum or tungsten is selectively deposited only on these metals by chemical vapor deposition to form an electrode. A method for manufacturing an electrode wiring in which the wiring is formed with f:% characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3071883A JPS59158516A (en) | 1983-02-28 | 1983-02-28 | Manufacture of electrode and wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3071883A JPS59158516A (en) | 1983-02-28 | 1983-02-28 | Manufacture of electrode and wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59158516A true JPS59158516A (en) | 1984-09-08 |
Family
ID=12311423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3071883A Pending JPS59158516A (en) | 1983-02-28 | 1983-02-28 | Manufacture of electrode and wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59158516A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089442A (en) * | 1990-09-20 | 1992-02-18 | At&T Bell Laboratories | Silicon dioxide deposition method using a magnetic field and both sputter deposition and plasma-enhanced cvd |
| KR100253561B1 (en) * | 1992-08-28 | 2000-05-01 | 김영환 | Method of depositing w on oxide of semiconductor device without adhesion layer |
-
1983
- 1983-02-28 JP JP3071883A patent/JPS59158516A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089442A (en) * | 1990-09-20 | 1992-02-18 | At&T Bell Laboratories | Silicon dioxide deposition method using a magnetic field and both sputter deposition and plasma-enhanced cvd |
| KR100253561B1 (en) * | 1992-08-28 | 2000-05-01 | 김영환 | Method of depositing w on oxide of semiconductor device without adhesion layer |
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