JPS59154962U - level compression circuit - Google Patents
level compression circuitInfo
- Publication number
- JPS59154962U JPS59154962U JP4768183U JP4768183U JPS59154962U JP S59154962 U JPS59154962 U JP S59154962U JP 4768183 U JP4768183 U JP 4768183U JP 4768183 U JP4768183 U JP 4768183U JP S59154962 U JPS59154962 U JP S59154962U
- Authority
- JP
- Japan
- Prior art keywords
- signal output
- signal
- output terminal
- compression circuit
- level compression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Picture Signal Circuits (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例を示す回路図であり、第２図は上記従来
例の動作特性を示す特性線図である。第３図は本考案に
係るレベル圧縮回路の一実施例を示す回路図であり、第
４図は上記従来例の動作特性と実施例の動作特性とを比
較して示す特性線図である。
３０・・・電圧信号源、４０・・・バッファ増幅回路、
５０・・・ガンマ補正回路、６０・・・ホワイトクリッ
プ回路、６．１．６２・・・ホワイトクリップ回路を構
成するトランジスタ、８０・・・信号出力端子。FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a characteristic diagram showing the operating characteristics of the conventional example. FIG. 3 is a circuit diagram showing an embodiment of the level compression circuit according to the present invention, and FIG. 4 is a characteristic diagram showing a comparison between the operating characteristics of the conventional example and the operating characteristics of the embodiment. 30... Voltage signal source, 40... Buffer amplifier circuit,
50... Gamma correction circuit, 60... White clip circuit, 6.1.62... Transistor constituting the white clip circuit, 80... Signal output terminal.
Claims (1)
ンに設けた信号出力端子に接続したガンマ補正回路と、
上記信号出力端子にコレクタが接続されているとともに
基準電圧がベースに印加されている第１のトランジスタ
と上記電圧信号源からの出力される信号と逆相の信号が
ベースに供給される第２のトランジスタにて構成した差
動増幅回路を備え、上記差動増幅回路の利得に応じて設
定自在な圧縮率にて、上記電圧信号源から出力される信
号の所定レベル以上を圧縮して信号出力端子より出力す
ることを特徴とするレベル圧縮回路。a gamma correction circuit connected to a signal output terminal provided on a signal output line of a voltage signal source having an output impedance;
a first transistor whose collector is connected to the signal output terminal and whose base is applied with a reference voltage; and a second transistor whose base is supplied with a signal having the opposite phase to the signal output from the voltage signal source. A signal output terminal is provided with a differential amplifier circuit configured with transistors, and compresses the signal output from the voltage signal source at a predetermined level or higher at a compression rate that can be set according to the gain of the differential amplifier circuit. A level compression circuit characterized by a higher output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4768183U JPS59154962U (en) | 1983-03-31 | 1983-03-31 | level compression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4768183U JPS59154962U (en) | 1983-03-31 | 1983-03-31 | level compression circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59154962U true JPS59154962U (en) | 1984-10-17 |
| JPH0117891Y2 JPH0117891Y2 (en) | 1989-05-24 |
Family
ID=30178228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4768183U Granted JPS59154962U (en) | 1983-03-31 | 1983-03-31 | level compression circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59154962U (en) |
-
1983
- 1983-03-31 JP JP4768183U patent/JPS59154962U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0117891Y2 (en) | 1989-05-24 |
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