JPS59153382A - Image pickup device - Google Patents

Abstract

PURPOSE:To save power consumption and to prevent effectively blooming by stopping the supply of high frequency pulse for anti-blooming in reading and recording the information from an image pickup means. CONSTITUTION:Carrier transfer pulses phiP1-phiP6 formed from a timing signal from clock generators CGs 9, 8 and an anti-blooming pulse phiAB are applied to a CCD image sensor 100 via a driver 7. An output of the sensor 100 is amplified 10, is subject to a prescribed correction at a process circuit 11 and led to a head 13 via a gate 12 and recorded on a recording medium 14. After a pulse from a trigger circuit 19 is outputted, until the first vertical synchronizing signal VD is obtained from the CG9 and then the next signal VD is obtained, the gate 12 is opened and a signal for one field's share is recorded on the medium 14. The power consumption is saved by stopping the pulse phiAB from the CG8 via an inverter 20 during this period and the blooming hardly occurs in a recorded video signal.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to an imaging device that can effectively suppress blooming. It has been considered to eliminate excess gear by providing an overflow drain or by utilizing surface recombination.

In particular, the latter method has advantages such as high sensitivity because it does not sacrifice the aperture ratio within the light receiving surface, and horizontal resolution that can be improved because it can improve the degree of integration.

1 to 3 are diagrams for explaining a blooming prevention method using such surface recombination, and FIG. 1 is a front view of a general frame transfer type CCD.

In the figure, reference numeral 1 denotes a light receiving section, which is composed of a plurality of photosensitive vertical transfer registers.

Further, numeral 2 consists of a plurality of vertical transfer registers shielded from light by a storage section. Reference numeral 3 denotes a horizontal transfer register which simultaneously shifts the information in each vertical transfer register of the storage section 2 by one bit. can be obtained.

Generally, the information formed in the vertical +M registers of the light receiving section 1 is vertically transferred to the storage section 2 during the vertical Iμ blanking period in the standard television system, and then horizontally during the next vertical scanning period. The data is sequentially read out from the transfer register 3 one row at a time.

Here, it is assumed that the light receiving section 1, the storage section 2, and the horizontal transfer register 3 are each driven in two phases, and the respective transfer electrodes are set to Pl,
P2, Pl, P4, P5, Pa, and their transfer locks are φ□, φP2sφP3, φP4, φ11, φP6,
shall be.

FIG. 2 is a diagram showing the potential profile under such transfer electrodes P, -P. For example, electrodes P2, P4, Pa
Apply low level voltage -■1 to P3 I
When a high-level voltage V2 is applied to P5, a potential as shown by the solid line in the figure is formed, and the electrodes P+ and P3
, P5, and apply a low level voltage V to the electrodes P2. P
, , When a high level voltage 2 is applied to Pa, a potential as shown by the broken line in the figure is formed.

Therefore, electrodes P+, Ps, P, and electrodes P2, P4, P,
By applying alternating voltages to and with opposite phases, carriers are sequentially transferred in one direction (rightward in the figure).

In addition, the dashed-dotted line in the figure shows the potential when a large positive voltage ■ is applied to the electrode, and since the well at this potential is inverted, excess carriers exceeding a predetermined amount recombine with majority carriers and disappear. Resulting in.

FIG. 3 is a diagram showing the shape of such electrode voltage and internal potential in the thickness direction of the semiconductor substrate 6. (1) For pressure V3, the potential well becomes shallow and excess carriers enter a second state where they recombine with majority carriers at the interface with the insulating layer.

On the other hand, when the electrode voltage is -1, the first state is the accumulation state, where majority carriers tend to gather around the interface, and this majority gear is supplied from, for example, a channel stopper region (not shown). For example, with a barrier formed by applying voltage -Vl to electrode P2, frost: pressure -■1 is applied to electrode PI.
By alternately applying Since the accumulation state and the inversion state must be formed alternately and at high speed in the semiconductor substrate, there is a problem in that the 111 power consumption is large. However, when such pulse control is performed at high speed, there is a problem in that noise caused by the pulses is mixed into the signal.

(Objective) It is an object of the present invention to provide an imaging device that can overcome the drawbacks of the prior art.

Another object of the present invention is to provide an imaging device that can effectively prevent pluming and has a high power saving effect.

(Example) Hereinafter, the present invention will be explained in detail based on Examples.

FIG. 4 is a diagram showing a first embodiment of the configuration of the imaging device q of the present invention, and in the figure, 100 is an image sensor as an imaging means.
It may be a CCI (as shown in FIG. 1) or an MO8 type XY address image sensor.

In this embodiment, the frame transfer type CC shown in the first diagram is
When D is used, the eyes become brighter.

7 are transfer pulses φP1 to φ1.7 necessary for this CCD image sensor transfer. and a driver circuit as an indulgence means for supplying anti-pluming pulses φAB, which will be described later, and 9 is a J-th clock generator that forms timing signals of φPI to φP among these pulses. Reference numeral 8 denotes a second clock generator as recombination control means. Based on the timing signal of the clock generator 8, the driver circuit 7 forms an anti-pluming pulse φAB and supplies it to the electrode P1 of the image sensor. .

The output of the image sensor 100 is amplified by the amplifier 10, then subjected to gamma correction, aperture correction, etc. in the process circuit 11, and guided to the head 13 via the gate 12, where it is recorded on the recording medium 14. Here, the head 13, medium 14, etc. constitute a recording means.

A trigger circuit 19 generates a pulse signal by operating an operation switch (not shown). This trigger circuit is for selectively recording one field or one frame image as described later by operating this operation switch at an appropriate timing while monitoring the output of the process circuit 11 on a video monitor, for example. It is.

In synchronization with the fall of the pulse output of the trigger circuit, as shown in FIG.
A high level signal is output only during the vertical interval.

16 is a vertical synchronization pulse V from the clock generator 9
This is a one-shot circuit that outputs a high-level pulse in synchronization with the falling edge of D, and the output of this one-shot circuit 16 is input to the clock input terminal of the D-7 lip/70 tube.

Therefore, as shown in FIG.
is opened, and the signal for one field is recorded on the recording medium 14 via the head 13. Note that the recording medium 14 rotates in phase synchronization with the vertical synchronization signal.

Further, while this gate 12 is open, the second clock generator 8 is stopped via the inverter 20.

-Here, the 7-lip flop 17, the inverter 20, etc. constitute a stopping means.

Furthermore, as shown in FIG. 5, the anti-pluming pulse φA
B is designed not to operate during the vertical transfer period.

Also, B to pulse φ is 1 to pulse φP1 or pulse φP2.
Switching control is performed in the driver 7 so that the fields are alternately superimposed. Also, pulse φ
P1 and φP! The phase is shifted by one field, and therefore the positions of the potential well and potential barrier are shifted by the distance of the electrodes P, , P, for each field. This creates interlacing. Note that the pulse φAB is superimposed on the electrode that does not form a potential barrier.

In this embodiment, the formation of the pulse φAB is stopped only while the output of the image sensor is being recorded, but if the configuration is such that the next recording operation is not possible for a predetermined period of time even after recording is completed, Alternatively, the pulse φAB may be stopped for an appropriate period of time, for example, several (vertical periods) after the start of recording.

Additionally, since there is generally an operational time lag between the end of a recording operation and the start of the next recording operation, it is more practical to configure the pulse φAB to be stopped for a predetermined period of time after the start of recording as described above. It is also a target.

Furthermore, in this embodiment, a case has been described in which only one field of a continuously formed video signal is extracted and recorded. Needless to say, it is also effective in a configuration in which the above image is read out and recorded as image information of two fields interlaced with each other, for example.

In this embodiment, the gate 16 is opened to keep φAB at the ○ level for a predetermined period of time after the start of recording, but during this period, for example, a potential of -■ is applied except for the vertical transfer period. It's okay to stay. In that case, there is an effect that dark current is less likely to occur.

(Effects) Since the supply of high-frequency pulses for anti-pluming is stopped with the start of recording of the output of the signal read out from the imaging means, power consumption can be saved. Moreover, pluming is less likely to occur in the video signal to be recorded.

Furthermore, since noise caused by the anti-pluming pulse is not generated during the recording period, the S/N ratio of the recording signal is not impaired.

[Brief explanation of the drawing]

Figure 1 shows an example of an image sensor, Figure 2 shows an example of the potential profile under each electrode, Figure 3 shows the potential characteristics according to the fit electrode potential, and Figure 4 shows the main FIG. 5 is a diagram showing an example of the configuration of the imaging device of the invention, and FIG. 5 is a drive timing diagram of the configuration shown in FIG. P l” P6...electrode, 5...
Insulating layer, 6...Semiconductor substrate. Patent Applicant Canon Co., Ltd. Agent Gi Marushima −−5i −11−−−−−−−−−−↓− h～８ 5 6

Claims (1)

[Claims] Imaging means for converting an optical image into distribution information of a minority gear; a first state in which majority carriers are accumulated within the imaging means; a control means for periodically forming a second state to be combined; a reading means for reading out the information in the converting means; and selectively recording information for a predetermined period from among the information read by the reading means. An imaging device comprising: a recording device; and a stopping device that stops the control device when the recording device starts recording.