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JPS59152656A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59152656A
JPS59152656A JP2716883A JP2716883A JPS59152656A JP S59152656 A JPS59152656 A JP S59152656A JP 2716883 A JP2716883 A JP 2716883A JP 2716883 A JP2716883 A JP 2716883A JP S59152656 A JPS59152656 A JP S59152656A
Authority
JP
Japan
Prior art keywords
film
wiring
side surfaces
leads
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2716883A
Other languages
Japanese (ja)
Inventor
Shigeru Kagiyama
鍵山 滋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2716883A priority Critical patent/JPS59152656A/en
Publication of JPS59152656A publication Critical patent/JPS59152656A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49572Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate a bonding without shortcircuit and a standardization of a semiconductor device by forming the device of a film carrier having a plurality of wiring leads on both side surfaces of a film and a semiconductor chip in which wiring leads and electrodes are connected. CONSTITUTION:Wiring lead 2, 2' and bonding pads 3, 3' connected to one ends of the leads are provided on both side surfaces of a film 1. A resin film having 100mum of thickness is cut in width of 30mm., sprocket holes 7 and pellet holes 4 are punched at the film, and copper foils 8 are thermally press-bonded to both side surfaces of the film. Then, photoresists are coated on both side entire surfaces of the foils 8, and exposed via a pattern mask simultaneously on both side surfaces at every one frame. Unecessary copper is removed by etching to form a wiring pattern. Then, a gold plating is formed on the surface of the copper. Eventually, a wiring portion shortcircuited for plating is punched to obtain a film carrier.

Description

【発明の詳細な説明】 本発明は、半導体装置に関し、特にフィルムキャリアを
使用した半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device using a film carrier.

従来、半導体チップのパッケージへの実装方法として、
アルミニウム糾又は金線を用いて、直接ケース又ハベー
スリボンにボンディングするワイヤーボンディング法と
、樹脂フィルム上にバターニングされた金属配線パター
ンをもつフィルムキャリアにボンディングした後、改め
てパッケージに実装する方法とが用いられている。フィ
ルムキャリアを用いる方法−1生産効率の悪い多ビンの
半導体チップのボンディングや、1つの基板にいくつも
の半導体チップを実装して高集積化をはかる場合によく
適用される。
Traditionally, as a method for mounting semiconductor chips on packages,
A wire bonding method uses aluminum or gold wire to bond directly to the case or Habase ribbon, and a method involves bonding to a film carrier with a patterned metal wiring pattern on a resin film and then mounting it on the package again. is used. Method using a film carrier - 1 This method is often applied to the bonding of semiconductor chips in multiple bins, which is inefficient in production, or when a number of semiconductor chips are mounted on one substrate to achieve high integration.

フィルムキャリア方式の場合、電気選別は通常チックを
フィルムキャリアにボンディングした後の、クースヘ実
装する前に行なわれるので、テスター側の電気テスト用
配線ビンとコンタクトをとるパッドかフィルム上にパタ
ーニングされている。
In the case of the film carrier method, electrical screening is usually performed after the tick is bonded to the film carrier and before mounting on the coupe, so the pad that makes contact with the electrical test wiring bin on the tester side or patterned on the film is used. .

このパッドは、半導体チップを中心に、四方に又は放射
状に配置されているが、チップの・端子数が増えるにつ
れてパッド−パッド間、ノ々ツドーリード間に距離が短
縮されさらに、1つの半導体チップに必要なフィルム面
積も増大する。そのため、従来、選別工程でコンタクト
不良によるショート又はオープン等の不良モードを発生
し易い上、1駒分のフィルム面積が使用ピン数によって
異なり、フィルムサイズの標準化が計れないという欠点
があった。
These pads are arranged around the semiconductor chip in all directions or in a radial pattern, but as the number of terminals on the chip increases, the distances between pads and between the leads are shortened, and even more The required film area also increases. Therefore, in the past, failure modes such as short circuits or opens due to contact failures are likely to occur during the sorting process, and the film area for one frame varies depending on the number of pins used, making it impossible to standardize the film size.

第1図は従来のフィルムキャリアに接続した半導体チッ
プの要部上面mlである。
FIG. 1 is a top view of the main part of a semiconductor chip connected to a conventional film carrier.

フィルム1には配線リード2が複数本設けられ、各配線
リード2の一端にはボンディング用パッド3が設けられ
ている。フィルム1にはベレットホール4が設けられて
いる。このベレットホール4内に半導体チップ−5を置
き、半導体チップの電極6.5と配線2とを接続する。
A plurality of wiring leads 2 are provided on the film 1, and a bonding pad 3 is provided at one end of each wiring lead 2. A bullet hole 4 is provided in the film 1. A semiconductor chip 5 is placed in this bullet hole 4, and the electrodes 6.5 of the semiconductor chip and the wiring 2 are connected.

このようなフィルムキャリアにおいて、半導体チップの
電極6の数が多くなるとパッド3−パッド3間の距離は
狭められ、さらにバンド面積も小さくなるので、電気選
別の際、コンタクト乏とるビンがずれて、他のパッドや
り一部に短絡し易いという欠点を生ずる。
In such a film carrier, as the number of electrodes 6 on the semiconductor chip increases, the distance between the pads 3 becomes narrower, and the band area also becomes smaller. This has the disadvantage that it is easy to short-circuit to some other pads.

本発明は上記欠点を除去し、配線リードの間隔、ポンデ
ィングパッドの間隔を広くして短絡を防ぎ、シカモ使用
ピン数を減らさないフィルムキャリアを使用する半導体
装置を提供するものである。
The present invention eliminates the above-mentioned drawbacks, and provides a semiconductor device using a film carrier that prevents short circuits by widening the spacing between wiring leads and the spacing between bonding pads, and does not reduce the number of pins used.

本発明の半導体装置ね、フィルムの両面に複数の配線リ
ードを有するフィルムキャリアと、前記配線リードと電
極とが接続さ庇た半導体チップとを含んで構成される。
The semiconductor device of the present invention includes a film carrier having a plurality of wiring leads on both sides of the film, and a semiconductor chip to which the wiring leads and electrodes are connected.

次に、本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described using the drawings.

第2図は本発明の一実施例の主要部の上面図である。FIG. 2 is a top view of the main parts of an embodiment of the present invention.

フィルム1の両面に配線リード2,2′とこれの一端に
接続するポンディングパッド3,3′が設けられる。番
号2.3はフィルムの表面に設けられたもの、番号2’
、3’はフィルムの裏面に設けられたものを示す。この
ように配p リード及びポンディングパッドを両面に設
けると、片面のパッド数は半分で済むのでバッド面積も
大きくでき、またパッド間距離も広げられるので、ボン
ディング作業も容易となり、短絡も防止できる。更に、
パッド面積を適当に選定することKよシフィルムキャ 
  −リアの1駒のサイズの標準化も可能となる。
Wiring leads 2, 2' and bonding pads 3, 3' connected to one end of the wiring leads 2, 2' are provided on both sides of the film 1. Number 2.3 is provided on the surface of the film, number 2'
, 3' indicate those provided on the back side of the film. By providing distribution leads and bonding pads on both sides in this way, the number of pads on one side can be halved, so the pad area can be increased, and the distance between pads can also be increased, making bonding work easier and preventing short circuits. . Furthermore,
Please select the pad area appropriately.
-It is also possible to standardize the size of the rear piece.

次に、本発明に使用するフィルム・、キャリアの製造方
法について説明する。
Next, a method for manufacturing the film and carrier used in the present invention will be explained.

第3図(a) 、 0))は本発明に使用するフィルム
キャリアの製造途中工程における平面図及び八−に断−
面図である。
FIG. 3(a), 0)) is a plan view and a cross-sectional view of the film carrier used in the present invention during the manufacturing process.
It is a front view.

まず、厚さ100μmの樹脂フィルムを幅35rrmで
切出し、スプロケットホール7、ペレットホール4を打
抜いた後フィルムの両面に銅箔8を熱圧着する。
First, a resin film with a thickness of 100 μm is cut out to a width of 35 rrm, sprocket holes 7 and pellet holes 4 are punched out, and then copper foils 8 are thermocompression bonded to both sides of the film.

次に1両面の銅箔全面にフォトレジストを塗布し、1駒
づつ両面同時にそれぞれのパターンマスクで露光する。
Next, photoresist is applied to the entire surface of the copper foil on both sides, and each frame is exposed to light using each pattern mask at the same time on both sides.

不要な銅をエツチングにより除去し、配線パターシを形
成する。しかる後、銅の表面に金メッキを施す。最後に
、メッキ用に短絡′してあった配線部分を打抜き、フィ
ルムキャリアを得る。
Unnecessary copper is removed by etching to form a wiring pattern. After that, gold plating is applied to the copper surface. Finally, the wiring portion that was short-circuited for plating is punched out to obtain a film carrier.

以上詳細に説明したように、本発明によれば、ホンディ
ングが容易で短絡がなく、標準化もしやすい。フィルム
キャリアを使用する半導体装置が得られるのでその効果
は大きい。
As described above in detail, according to the present invention, bonding is easy, there is no short circuit, and standardization is easy. The effect is great because a semiconductor device using a film carrier can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフィルムキャリアとこれに接続し九半導
体チップの費部上面図、第2図は本発明の一実施例の要
部平面図、第3図(a)、 (b)は本発明に使用する
フィルムキャリアの製造途中工程における平面図及び断
面図である。 1・・・・・・フィルム、2.2’・・・・・・配線リ
ード、3゜3′・・・・・・ポンディングパッド、4・
・・・・・ペレットホール、5・・・・・・半導体チッ
プ、6・・・・・・電極、7・・・・・・スプロケット
ホール、8・・・・・・銅箔。 第1区 第2図 ((2) 第 3 閃
Fig. 1 is a top view of a conventional film carrier and a semiconductor chip connected thereto, Fig. 2 is a plan view of a main part of an embodiment of the present invention, and Figs. FIG. 2 is a plan view and a cross-sectional view of a film carrier used in the invention during a manufacturing process. 1...Film, 2.2'...Wiring lead, 3゜3'...Ponding pad, 4.
... Pellet hole, 5 ... Semiconductor chip, 6 ... Electrode, 7 ... Sprocket hole, 8 ... Copper foil. 1st Ward Figure 2 ((2) 3rd flash

Claims (1)

【特許請求の範囲】[Claims] フィルムの両面に複数の配線リードを有するフィルムキ
ャリアと、前記配線リードと電極とが接続された半導体
チップとを含むことを特徴とする半導体装置。
A semiconductor device comprising: a film carrier having a plurality of wiring leads on both sides of the film; and a semiconductor chip to which the wiring leads and electrodes are connected.
JP2716883A 1983-02-21 1983-02-21 Semiconductor device Pending JPS59152656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2716883A JPS59152656A (en) 1983-02-21 1983-02-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2716883A JPS59152656A (en) 1983-02-21 1983-02-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59152656A true JPS59152656A (en) 1984-08-31

Family

ID=12213524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2716883A Pending JPS59152656A (en) 1983-02-21 1983-02-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59152656A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6377127A (en) * 1986-09-19 1988-04-07 Mitsubishi Electric Corp Semiconductor device
US4951098A (en) * 1988-12-21 1990-08-21 Eastman Kodak Company Electrode structure for light emitting diode array chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6377127A (en) * 1986-09-19 1988-04-07 Mitsubishi Electric Corp Semiconductor device
US4951098A (en) * 1988-12-21 1990-08-21 Eastman Kodak Company Electrode structure for light emitting diode array chip

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