JPS59152590A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a voltage limiter for lowering an external power supply voltage within a chip through a voltage limiter and applying the voltage to microscopic transistors within the chip.

[Prior art]

Regarding this voltage limiter system, we have already filed a patent application for the following content. Figure 1 is a patent application filed earlier in Japanese Patent Application Laid-Open No. 172761/1983, and is related to the memory array that determines the actual degree of integration of the chip 10. A fine MOS transistor 40 is used in the circuit, and the circuit is operated at a voltage VL obtained by lowering an external power supply voltage Vcc by a voltage limiter 13.

On the other hand, relatively large MO8I is used for other circuit areas including input/output interfaces that are not so related to integration density.
- This is an example in which the transistor 50 is used to apply Vcc and operate. Note that 20 is an oxide film, 30 is a diffusion layer, and 60 is a gate electrode of a transistor. This results in a highly integrated MOS memory that operates at Vcc when viewed from outside the chip! J
LSI becomes possible. A voltage limiter circuit for this method has already been proposed in Japanese Patent Application Laid-Open No. 57-172761, etc., but it is only a membrane type and there are no regulations regarding the size and number of stages of rectifying transistors, so it cannot be said to be a practical one. Ta. Further, the buffer circuit connected to the voltage limiter circuit has the disadvantage that it is difficult to set constants, and the required number of transistors is large, resulting in a large area occupied.

[Purpose of the invention]

One of the objects of the present invention is to provide a semiconductor device which is capable of stably maintaining the drive of a fine MO8 transistor and has a voltage limit circuit with a simple circuit configuration.

Another object of the present invention is to provide a semiconductor device that can apply a stable voltage to a fine MO8 transistor regardless of transient fluctuations in load.

[Summary of the invention]

One of the features of the present invention is that it has an output voltage characteristic that is a composite of convex and concave shapes with respect to the external power supply voltage, and that the nominal value of the external power supply voltage has a gentle slope between the convex shape and the concave shape. The present invention is provided with a voltage limiter circuit having an output voltage characteristic set in each section.

The main difference lies in the provision of a fa circuit. More specifically, this will be clarified in the description of the following embodiments.

[Embodiments of the invention]

FIG. 2 shows a specific example of the voltage limiter, and FIG. 3 shows an example of its characteristics. As shown in FIG. 3, the dependence of the limited voltage VL on the external power supply Vcc is expressed by a combination of three straight lines. In other words, when Vcc is from O to V, from point o to -, the rectifier QllQ2, Qs and Qt are cut off, so the gate voltage Va of Qo is set to Vcc+Vth.
If (V th : ) threshold voltage of the transistor), then VCC is outputted. When Vcc becomes more than Vo, Q t l Q21Q3 turns on, and as a result, the gate voltage of Qt also becomes more than V t b , and QL
is turned on. Therefore, VL is determined by the ratio of conductance between Qo and Qt, and when Vcc is higher than Vo, it becomes a straight line with a small slope as shown in the figure. However, Vc
When c reaches the 5.5V point, the voltage difference applied to Q1' and Q2' increases, resulting in Q1' and Q2' as well as Qt'
is turned on, and vL increases by that amount.

Therefore, as shown in the figure, the VL straight line has a large slope at Vcc of 5.5V or more. If the normal operating power supply voltage (nominal voltage) Vcc is 5V, then Figure 3 has ideal characteristics for LSI design, as shown below, and Figure 2 satisfies these ideal characteristics. It can be seen that this is an example.

First, the desired VL for Vcc near the nominal voltage 5V.
Describe the characteristics. In this Vcc region, ■1, V
A smaller slope with respect to cc is more convenient for circuit design. This is because, in general, the operating speed of a MO8I-transistor is strongly influenced by the operating voltage, so the speed of a circuit that uses VL as the operating voltage within the chip will increase as VL is stabilized and the slope is smaller. The speed must stabilize. FIG. 2 clearly shows a circuit with a small slope near the nominal voltage.

Even though the nominal voltage is 5V, a design is usually made that guarantees operation even at a much lower voltage than 5V. Therefore, let us examine Vr and characteristics required in such a low voltage region of Vcc in Study 1-. Generally the nominal voltage is 5
Even in the field of V, a wide Vcc voltage margin is required to allow operation even at a low voltage of approximately Vcc to 3 V, considering manufacturing process variations, power supply voltage variations, and temperature variations. There are also other reasons why operation must be guaranteed even at Vcc~3V. In other words, during a power outage, the battery can
When backing up the power supply Vcc of the SI chip, due to the current capacity limit of the battery, one method is to lower Vcc from 5V to about 3V, reduce the current of the LSI chip itself, and increase the battery backup amplifier time. It will be done. In this case, it is necessary to operate the L''SISI itself even when Vcc is ~3V.For the above reasons, it is necessary to stabilize the circuit operation even when Vcc is around 3V, but in this case, the problem is that the This is a circuit that operates with a voltage of ■.In other words, if VL becomes too low, the operation of VL-related circuits will become unstable first.In other words, it is better that VL is as large as possible.The maximum value of VL Since Vcc is Vcc, it is desirable for the voltage limiter circuit to have a circuit configuration in which VL=VCC when Vcc is on the low voltage side.

In order to realize this, we actually need to use the transistor Qo in Figure 2.
This means that the gate voltage of is set to Vcc + V th. However, it is clear that Vo does not need to be fixed at Vcc + V th and can be set to a voltage higher than this.

Next, it is necessary to perform the knee thrust described below at a voltage considerably higher than the nominal voltage, and the Vt and characteristics required to effectively perform this will be discussed. An aging test is a test in which a high voltage stress higher than the nominal voltage is applied to each transistor in the chip, and chips containing transistors with abnormally low breakdown voltage are removed in advance. In this case, if the voltage stress conditions applied to the large size transistors operating at Vcc and the voltage stress conditions applied to the small size transistors operating at VL become unbalanced, effective aging testing will not be possible. That is, if voltage stress is applied at Vcc - 8, then 8, which is 1.6 times the nominal voltage, will be applied to a large transistor. But if V
If the b characteristic has a small slope in the vcc>5V region, then vc
Since there is no difference in VL when c is 8V and 5V, small transistors have a
) will not be subject to effective stress. To solve this problem, as shown in FIG. 3, it is desirable to use a straight S in which the slope of the VL characteristic becomes large at a certain Vcc of 5 V or more.

Actually, the transistors Q1', Q2' l Qt in Figure 2
The circuit consisting of ' was a useless circuit.

From the above, with respect to the nominal voltage, in the Vcc region below this, a convex Vb characteristic (VL can be considered to be convex in the Vc-c range of 0 to 5 V in Figure 3) is given, and in the Vcc region above this, It can be seen that it is sufficient to provide a concave VL characteristic. Alternatively, in a voltage limiter circuit that has a convex Vt characteristic in the low Vcc region and a concave Vt characteristic in the high Vcc region,
It can be said that the nominal voltage may be set at the midpoint between the convex and concave Vs. Here, the nominal voltage is assumed to be, for example, 5V, but it goes without saying that any value may be used for reasons of design. The user can also set the nominal voltage to I, SI.
Even if you use , the power supply voltage will fluctuate. If this permissible fluctuation range, for example, a fluctuation range including ±10 inches, is set within the second linear region as shown in Figure 3, an LS with stable operation can be achieved.
I can design.

In Figure 2, Ql, which is a rectifying element (diode),
Three Q2 and Q3 are connected in series, and the switch is Q, / and Q.
The reason why two 2' are connected in series is as follows. In general, V in FIG. is nV t l+ (n'Ql
+ Q21 Q, 3', etc. are expressed as the number of stages connected in series to the ground (n = 3 in Figure 2), and the intersection of the second straight line and the third straight line (5, 5 in the figure) V)
The voltage difference between VL and the corresponding Vcc at
h (m: q, ', Qz', etc. diodes are V
The number of stages connected to the cc terminal and the 'VL terminal, n in Figure 2
=2). If the vL characteristic changes significantly due to manufacturing variations in the threshold voltage V t I+- of the transistor, the operation of the entire LSI becomes unstable. In particular, since the variation in Vth increases by n or m times, it is important to keep the variation in Vth small and to set n and m to small values. In order to reduce the variation in Vt)+, it is better to set the channel length as large as 5 μm as shown in FIG. 2. In other words, in the chip shown in FIG.
Transistors in the 2 .mu.mn range are used, and the channel length is tightly controlled to accommodate such small transistors. This is because, in general, the threshold voltage increases as the channel length increases, so it is necessary to strictly control the variation in channel length of micro transistors of 1 to 2 μn1 to keep the variation in threshold voltage within a certain tolerance range. This is to prevent this from happening. This variation in threshold voltage is proportional to the variation ratio in the channel length of the transistor, so if the channel length is set to 5 μm as shown in Figure 2, even if the channel length varies, it will be possible to use a long channel. Normally, Vth of a transistor with a channel length of 1 to 2 μm in a memory array or a drive circuit is set to about 1/1O of the nominal voltage Vcc. In this case, the voltage Vth of the long-cell transistor in the voltage limiter becomes approximately one-fifth of the nominal voltage Vcc.

In other words, if the nominal voltage is 5μ, the channel length is 5μ.
The Vth of the transistor m is 1v. Therefore, as mentioned above, if you set Vo = 3V, n = 3 automatically.
Next, we will discuss the number of stages of the transistors Q l/ and Q 2/ in Fig. 2 that contribute to the third straight line (V≧5.5 V > in Fig. 3. Vcc at the intersection of the straight line and the third straight line has a minimum value when the slope of the second straight line is zero.This minimum value must be smaller than the nominal voltage 5■, so n =3;”Vth=
If IV, then (n0m)Vth≧5V・°・m) 2 . As a result, as shown in FIG. 2, two stages of diodes are connected in series. In reality, the constants of each transistor in Figure 2 are set so that the slope of the second straight line in Figure 3 is not zero, so the V at the above intersection
cc moves to the high voltage side and its value becomes 5.5■.

For convenience of calculation, in Figure 2, V o ” Vcc +
Assuming Vth, Vc>Vcc +Vth('
) range, then Vc <, V o and VL=VC
It is obvious that Vc can be arbitrarily selected within this range.

The memory array related circuit shown in FIG. 1 becomes a large capacitive load when viewed from the voltage IJ transmitter.

Moreover, this capacitive load causes transient fluctuations depending on the operating conditions of the memory array related circuit. In other words, since a transient current flows, the limiter circuit is required to have the ability to absorb this transient current, that is, the ability to drive a load, in order to supply a stable vL.

However, the circuit of FIG. 2 is not capable of driving such a large load and is therefore effective only when the load capacitance is small. Therefore, in the above case, a buffer circuit is connected to the voltage limiter circuit shown in FIG. 2, and the large load driving capability of this buffer circuit is utilized to drive a large capacitive load.

Therefore, some embodiments of this buffer circuit will be described below.

FIG. 4 shows an example of a circuit for supplying a stable voltage VL to a large capacity load CL by utilizing the output voltage VL+Vth of one end 2 of the rectifying element connected between the L terminal 1 and Vcc. Transistor Qt' can be regarded as a type of buffer circuit. If the conductance and channel width of this transistor are made sufficiently large, and its threshold voltage is made to match the Vth of the transistor Q3', then
The output voltage value of the transistor Qt' is equal to the VLO value of the terminal 1, and the load driving ability is also equal to the VLO value of the terminal 1. Here are the normal Vcc usage conditions. Assuming that the nominal condition is 5V, the voltage characteristics of the output terminal 1 of the voltage limiter may be set as shown in FIG. That is, the terminal voltage characteristics are made to be a combination of four straight lines as shown in FIG.

When vcc is from O to Vo, it is transistor Q. Takeransistor Q1'+ Q2'I Q11' is also conductive, and 72
In the above, the transistors Q, //~Q6'' are also set to conduct.If the nominal voltage of Vcc is set to be between Vl and V2 above, then the transistors Since Ql' to Q3' are conductive, a stable voltage of yVL-1-V'th is applied to the gate of the output transistor Qt' as described above.However, in the example of FIG. , the threshold voltage of all transistors is assumed to be 0.5V.

As mentioned above, the normal threshold voltage is about IV, but it is easy to selectively lower the threshold voltage using ion implantation technology or the like. By using the technique of selectively setting the threshold voltage in this way, six transistors Ql//~Q6'' of the transistors in FIG.
It is also possible to replace it with three transistors having a threshold voltage IV.

This allows a voltage limiter to be configured with a small number of transistors, that is, with a small occupied area.

FIGS. 6 and 7 show examples of buffer circuits and their timings that are effective when the load capacity is small and the load undergoes transient fluctuations. Simplified, the load LC for the limiter circuit including the buffer circuit generally operates as follows.

In other words, the load LC connects the node 6, which is discharged by the transistor Qt2 when the pulse φ2 is turned on, with the pulse φl.
is turned on and charged by transistor Qll. During this charging, an excessive transient current flows through node 5, but if the voltage limiter itself does not have current supply capability, sufficient voltage VL cannot be supplied to node 5 or 6. In FIG. 6, the output voltage at node 10 is set to V L +2Vth so that the steady voltage at node 5 becomes VL after passing through transistors Q, . . . Q4.

To avoid this, the output is taken out from the source of the transistor Ql' shown in FIG. Further, at the time when φl is on and a transient current flows to node 5, the gate of transistor Q4 is boosted to increase the current supply capability of C4. That is, since the gate of Q9 is charged to a high level at Qa + Q8 by φ2, the voltage at node 2 is boosted through C1 by the application of φ1, and then QIO is turned on by φ1', which is then applied. Result node 2 is again V
It becomes L+V th. The feature of this circuit is that the circuit is simple, and the voltage boosting period of node 2 can be arbitrarily set by the application timing of φ1'. However, since there is no current path flowing from node 1 to ground, power consumption can be reduced.

〔Effect of the invention〕

As described above, the present invention makes it possible to provide a voltage limiter circuit that can stably operate a fine MO:''S transistor even under a relatively high external power supply voltage.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the overall configuration of a voltage limiter system which is the basis of the present invention, FIGS. 2 and 3 are main circuits and their characteristic diagrams of an embodiment of the present invention, and FIG. FIG. 5 is a main circuit and its characteristic diagram of another embodiment of the present invention,
6 and 7 are main circuits and their characteristic diagrams of still another embodiment. LM...Voltage limiter, Qh + C2+ C3+
Ql'IQz, Qz'...MOS transistor. Ku ≦ +1 Ku (A)7A

Claims (1)

[Claims] In a semiconductor device that has a built-in voltage limiter circuit that has an output voltage characteristic that is a combination of convex and concave shapes with respect to the external power supply voltage, the nominal value of the external power supply voltage is set between the convex and concave shapes. A semiconductor device characterized by: