JPS59150439A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59150439A JPS59150439A JP59007074A JP707484A JPS59150439A JP S59150439 A JPS59150439 A JP S59150439A JP 59007074 A JP59007074 A JP 59007074A JP 707484 A JP707484 A JP 707484A JP S59150439 A JPS59150439 A JP S59150439A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- main surface
- island
- width
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000005530 etching Methods 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は位、１脂封止型半導体装置に係り、特に；ｌ
ｌ７Ｎ・体チップが取りつけられるリードフレームの改
良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to (1) a fat-sealed semiconductor device, and in particular;
This invention relates to an improvement in a lead frame to which a 17N body chip is attached.
柄指封止型半導体装置は、長尺の金属薄板をエツチング
加工やプレス加工をして、半導体チップを取りつける支
持域であるアイランドと、半導体チップへの電気信号の
入出力経路となるインナーリードとアウターリードとが
設けられたリードフレームを用いて普通形成されている
。A finger-sealed semiconductor device is made by etching or pressing a long thin metal plate to form an island, which is a support area for attaching a semiconductor chip, and an inner lead, which is an input/output path for electrical signals to the semiconductor chip. It is usually formed using a lead frame provided with outer leads.
一方半導体チツブは半導体ウエノ・からの収率を向上さ
せるためにも、半導体チップ自体の寸法が縮少される傾
向にある。このような傾向に従って半導体チップが取り
つけられるリードフレームは多リード品およびインナー
リードのワイヤーボンディングに対する適正な先端位置
および所定表面幅が要求されるものである。On the other hand, the size of semiconductor chips themselves tends to be reduced in order to improve the yield from semiconductor chips. In line with this trend, lead frames to which semiconductor chips are attached are required to have multiple leads and inner leads with appropriate tip positions and predetermined surface widths for wire bonding.
しかしながらエツチングによ−ってリードフレームを金
属薄板から製造するときには、そのインナーリードの先
端部の形状は金属薄板の板厚と同程度の抜き落し幅が必
要であるため、アイランドに取）つけられた半導体チッ
プの＝ｅｔ極とインナーリードの先端との距離は前記し
たリードフレーム製造時の条件に制限されて適正にワイ
ヤボンディングすることができる距離に短絡することは
出来なかった。したがって、ワイヤーボンディングする
ときワイヤの長さを長くしなければならず、封止時にボ
ンディングワイヤとボンディングワイヤ、ボンディング
ワイヤとり゛−ドフレームのアイランド、ボンディング
ワイヤとインナーリードの接触による短絡不良をひきお
こすことが多かった。However, when manufacturing a lead frame from a thin metal plate by etching, the shape of the tip of the inner lead requires a removal width comparable to the thickness of the thin metal plate, so it cannot be attached to an island. The distance between the =et pole of the semiconductor chip and the tip of the inner lead was limited by the conditions at the time of manufacturing the lead frame described above, and it was not possible to short-circuit the distance to a distance that would allow proper wire bonding. Therefore, when performing wire bonding, the length of the wire must be increased, which may cause a short circuit failure due to contact between the bonding wire and the bonding wire, between the bonding wire and the island of the lead frame, or between the bonding wire and the inner lead during sealing. There were many.
この発明はこのような不良を除去するためになされたも
のであって、半導体チップの接着されるリードフレーム
を改良して良好な特性を有する樹１宿封止型半導体装置
を提供するものである。すなわちインナーリードの先端
部分の形状を改良し、それによってインナーリードピッ
チが小さく出来、半導体チップが小さくなってもワイヤ
ボンディングを効率的に行って、特性の向上をはかるこ
とを特徴とするものである。The present invention was made in order to eliminate such defects, and it is an object of the present invention to provide a tree-sealed semiconductor device having good characteristics by improving a lead frame to which a semiconductor chip is bonded. . In other words, the shape of the tip of the inner lead is improved, thereby making it possible to reduce the inner lead pitch, and even when the semiconductor chip becomes smaller, wire bonding can be performed efficiently and characteristics can be improved. .
以下図面を参照してこの発明の実施例について説明する
。Embodiments of the present invention will be described below with reference to the drawings.
インナーリードの形状は従来は第１図、第２図に、示す
ような先端部をしていた。すなわち第１図は幅方向断面
図であり、第２図は長手方向断面図である。第１図にお
いてインナーリード１のワイヤボンディングされる主面
２と、これと反対側の主面３とはその幅が等しく、かつ
抜き落し幅、すなわち図にＡにて示す幅がリードのＭ、
ｇ ｔの半分にエツチングされて形成されている。捷
た第２図においてインナーリード１の主面２と他の主面
３とはその先端からアイランド（図示せず）に至る距離
は共に等しく、かつ抜き落し幅Ｂもリードの厚さｔの半
分にエツチングされて形成されている。Conventionally, the shape of the inner lead was a tip portion as shown in FIGS. 1 and 2. That is, FIG. 1 is a cross-sectional view in the width direction, and FIG. 2 is a cross-sectional view in the longitudinal direction. In FIG. 1, the main surface 2 of the inner lead 1 to which wire bonding is applied and the main surface 3 on the opposite side have the same width, and the width of the lead, that is, the width indicated by A in the figure, is M of the lead.
It is formed by etching in half of g t. In FIG. 2, the main surface 2 of the inner lead 1 and the other main surface 3 have the same distance from the tip to the island (not shown), and the width B of the lead is half the thickness t of the lead. It is formed by etching.
これに対してこの発明では第３図、第４図に示すような
形状にリード先端部をエツチングして形成した。すなわ
ち第３図に示すように幅方向の断面において、ワイヤボ
ンディングされるインナーリード１１の主面１２はボン
ディングに必安な所定幅を有し、インナーリード】ｌの
（’（Ｊの主面１３１ｄ主面１２よりも幅がせまくエツ
チング形成３ ｉ’Ｌでいる。したがって最大幅部分Ｗ
はワイヤボンディングされる主面寄りとなり、かつ抜き
落し幅Ｃも工面１２側においてはリー ドの原さｔの半
分よりも小さくなっている。寸／ζ第４図に示すように
長手方向の断面においては、ワイヤボンディングされる
主面１２側の抜き落し幅りはリードの厚さｔの半分より
も小さく、かつ主面１２の先端１５が他の主面１３の先
端１３よりもアイランド（図示すず）に近く形成されて
いる。In contrast, in the present invention, the lead tips are etched to form the shapes shown in FIGS. 3 and 4. That is, as shown in FIG. 3, in the cross section in the width direction, the main surface 12 of the inner lead 11 to be wire bonded has a predetermined width necessary for bonding, and the main surface 131d of the inner lead ]l('(J) The width of the etching formation 3 i'L is narrower than the main surface 12. Therefore, the maximum width portion W
is closer to the main surface where wire bonding is to be performed, and the removal width C is also smaller than half of the lead original length t on the work surface 12 side. Size/ζ As shown in FIG. 4, in the longitudinal cross section, the removal width on the main surface 12 side to which wire bonding is performed is smaller than half of the lead thickness t, and the tip 15 of the main surface 12 is It is formed closer to an island (not shown) than the tips 13 of the other main surfaces 13.
このようにエツチングするには、たとえば第５図に示す
ように０２門の厚さの鉄ニツケル合金板（４２ａｌｌｏ
Ｖ） ２１の両面にホトレジスト２２を塗布し、各レジ
スト膜２２上に所定のリードを形成するためのパターン
を有するネガマスタ２３ 、２４をそれぞれ重ね、その
上にさらにガラス板の押え板２５を置いてのち露光する
。このマスク２３゜２４の光を１〜や断する部分の幅は
それぞれ異なり、エツチングされたときｉｉ’Ｊ 記の
リードの主面】２と主面１：３の幅になるようにもうけ
られている。次いで現像し、露光さ力、ていない部分、
これがインナーリード部分に対応するものであるが、こ
の部分を残してベーキング処理して硬化させる。次に両
面からエツチングして行き、マスクをとおしで露光され
た部分の合金板の両面から腐蝕が進んで行き、その合金
板の部分が取り除かれて、硬化したホトレジストを取り
除いて、リードフレームが形成されるものである。For etching in this way, for example, as shown in FIG.
V) Apply photoresist 22 to both sides of the resist film 21, stack negative masters 23 and 24 each having a pattern for forming a predetermined lead on each resist film 22, and further place a presser plate 25 made of a glass plate on top of the negative masters 23 and 24. Later exposed. The widths of the parts of the masks 23 and 24 that cut off the light are different, and when etched, they are made to have a width of 1:3 between the main surface of the lead shown in ii'J and 1:3. There is. Then it is developed and exposed to light, the parts that are not
This corresponds to the inner lead portion, and this portion is left and cured by baking. Next, etching is performed from both sides, corrosion progresses from both sides of the alloy plate in the area exposed through the mask, and the area of the alloy plate is removed and the hardened photoresist is removed to form the lead frame. It is something that will be done.
この発明によると％’Ｊ’；６図（この発明によるリー
ド先端部幅方向断面図）、第７図（従来のＩＪ−ド先端
部幅方向断面図）にて示すように、リード間には短絡し
ない間隙ｄをとればよいので、この発明のものは抜き落
し幅が小さくなっている（Ｃ＜Ａ）だめリードとリード
とのピッチは小さくすることができる。According to this invention, %'J'; Since it is sufficient to provide a gap d that does not cause a short circuit, the width of the lead-out is small (C<A) in the present invention, and the pitch between the leads can be made small.
たとえばリード有効幅ａを０２ｍｍ、Ｉ）−ド間隙ｄを
Ｑ、 ｌ ｍｍ 、リードのノ早さｔをＱ、 ２ ｍｍ
とシ２、この発明のものの抜き落し幅Ｃが］、 ／ ５
ｔ ：０．２ ／ ５ ｍｍ、従来のものの抜き落し
幅Ａが１／２ ｔ＝０．２／２ ｍｌｎであるの ０
２
で、この発明のもののピッチＰ＝０．２Ｘシ→７ ＋
ｏ、 ｉ＋ｕ＋ ０．２ ＸＬ＝０．３ ｓ朋となり、
従来のもののピッ５ ２
１０．２ ０．２ １チＰ’ ＝０
．２ ｘ −＋−＋ ｇ、ｌ ＋−，ｒＯ，２ｘ、＝０
．５肩ｍに比べ２
て・ノ＼となる。For example, the lead effective width a is 02 mm, the lead gap d is Q, l mm, and the lead speed t is Q, 2 mm.
2, the removal width C of this invention is ], / 5
t: 0.2 / 5 mm, the removal width A of the conventional one is 1/2 t = 0.2/2 mln 0
2, pitch P of this invention = 0.2X → 7 +
o, i+u+ 0.2 XL=0.3 s becomes friend,
Conventional pitch 5 2 10.2 0.2 1 inch P' = 0
．． 2 x −+−+ g, l +−, rO, 2x, = 0
．． Compared to 5 shoulder m, it becomes 2 te・ノ＼.
したがって、第８図に示す、Ｌうにインナーリード２０
先端が従来５．’Ｑ ｍｍ、” ｌピったものが、第９
図に示すよ９．イア ’Ｊ−−’Ｊ −）” ２１先イ
、ヵｉ ４．ｓｍｍ”−＋７詰めることができる。その
ためボンディング線の長さも短くすることができ、たと
えば４．８〜２．６ ｍｍでめった従来のものに比べ、
−この発明によると１２〜２．０ ｍｍと短くすること
ができ、改善ざｆｌ、プζ。Therefore, the L sea urchin inner lead 20 shown in FIG.
The tip is conventional 5. 'Q mm,' The one that hit is the 9th
As shown in the figure 9. Ia 'J--'J-)" 21 A, Kai 4.smm"-+7 can be packed. Therefore, the length of the bonding wire can be shortened, for example, compared to conventional wires that are only 4.8 to 2.6 mm.
-According to this invention, it can be shortened to 12 to 2.0 mm, resulting in improvements.
また第１−０図、第１１図に示すようにリードフレ−ム
のアイランド３１上Ｖこ取りつけられた半導体チッグ３
２の′成極とインナーリード３３どをボンディングする
とき、リード上のポンディング位１１′呆けきまってい
るので、ボンディング線３Ｇの長をがＪＱいとループダ
ウン（点場で示すような状態）が発生しやすくなるもの
であるが、前記したようにこの発明のものは線長を蝮く
することができるので、このような不具合はおこらない
。In addition, as shown in FIGS. 1-0 and 11, a semiconductor chip 3 is mounted on the island 31 of the lead frame.
When bonding the 2' polarization and the inner lead 33, etc., the bonding position 11' on the lead is not correct, so if the length of the bonding wire 3G is JQ, a loop down (as shown in the dot field) will occur. However, as mentioned above, the wire length of the present invention can be reduced, so such problems do not occur.
寸だボンディング線の長さが同じときは、従来のリード
先端部の形状（第１１図の３５）のときのボンディング
さ１＋、る主面におけるボンディング点から先端までの
距＃ｌＩより、この発明の先端部の形状（第１０層１の
３６）のときの距１ｉＩＰ１２の方が大となり、ループ
ダウン防止により有効となる。When the lengths of the bonding wires are the same, the distance from the bonding point to the tip on the main surface is #lI, which is the bonding depth 1+ for the conventional lead tip shape (35 in FIG. 11). The distance 1iIP12 when the tip end shape is (36 in the 10th layer 1) is larger, and is more effective in preventing loop-down.
このようにこの発明のものは、ワイヤポンディング干る
とき発生する短絡などの不具合を防止することができ、
特性の向トに寄−匂できるものである。In this way, the invention can prevent problems such as short circuits that occur during wire bonding.
This can affect the direction of the characteristics.
リード端部の形状１は前記しｔものばかりでなく、この
発明の要旨に従って、種々俵形構造のもの、たとえば断
面形状にて第１２図、第１３図に示すような（Ａは幅方
向の断面を示し、Ｂ ｌ：Ｉ：長手方向の断面を示す）
形状にエツチングして形成されたもの等が得られること
はいう寸でもない、。The shape 1 of the lead end part is not limited to the above-mentioned shape, but in accordance with the gist of the present invention, it can have a various barrel-shaped structure, for example, the cross-sectional shape as shown in FIGS. 12 and 13 (A is in the width direction). B l: I: shows a cross section in the longitudinal direction)
It is not impossible to obtain something that is etched into a shape.
この発明の半導体＠賄はワイヤーボンディングによる不
具合の発生を少なくし、半導体ペレットの小型化によく
対応できるきわめで工業的に有ＩＩＩな半導体装置であ
る。The semiconductor device of the present invention is an extremely industrially useful semiconductor device that reduces the occurrence of defects due to wire bonding and can respond well to miniaturization of semiconductor pellets.
【図面の簡単な説明】
＠１図、第２図は従来のリードフレーム・のりードの先
端の断面図にして，第】図ｌＩ」、幅方向の断面１／ｌ
．第２図は長手方向の断面図、第３図、・耶４図１４こ
の発明のリードフレームのリードの先端部のｌＩＪ『面
図にして、第３図は幅方向の断面図、第４図は長手方向
の断面図、第５図は金属板をエツチングする状態を示す
断面図、第６図はこの発明の複数本のリードの先端部の
幅方向の断面図、第７図は従来のリードの初数本の先端
部の幅方向の断面図、Ｆｌ＜８図は従来のリードフレー
ムのアイランドを除いて示したり一トフレームの中央部
の一部の平面図、第９図はこの発明のリードフレームの
アイランドを除いて示しだリードフレームの中央部の一
部の平面図、第１０図、第１１図はワイヤボンディング
された状態を示す側面図、第１２図Ａ。
Ｂ第１３図Ａ，Ｂはこの発明のリードの他の実施例の断
面図である。
ｌｌ・・・リードフレームのリード、１２．１３ ・リ
ードの主面．１５．１６・・・リード主面の先端、ａ・
・・ワイヤボンディングに必要なリード主面の所定＋１
Ｖ＾、ｔ・・・リードの厚さ、Ｐ・・・リードピッチ、
２０、２１・・リード（先端部）、：３ｌ・・リードフ
レームのアイランド、３２・・半導体一こし・ソト、３
３・・・リードフレームのリード、
３６・・・ボンディング線。
第１図 第３図
第５図
第６図
第７図
第８図[Brief explanation of the drawings] Figures 1 and 2 are cross-sectional views of the tip of a conventional lead frame/lead.
．． Figure 2 is a cross-sectional view in the longitudinal direction, Figure 3 is a cross-sectional view in the width direction, Figure 4 is a cross-sectional view of the tip of the lead of the lead frame of this invention, 5 is a sectional view in the longitudinal direction, FIG. 5 is a sectional view showing a state in which a metal plate is etched, FIG. 6 is a sectional view in the width direction of the tips of multiple leads of the present invention, and FIG. 7 is a sectional view of a conventional lead. Fig. 9 is a cross-sectional view in the width direction of the first few tips of the lead frame, Fl<8 is a plan view of a part of the central part of the conventional lead frame excluding the island, and Fig. 9 is a plan view of a part of the central part of the lead frame of the present invention. FIG. 12A is a plan view of a part of the central part of the lead frame, excluding the island of the lead frame; FIGS. 10 and 11 are side views showing a wire-bonded state; FIG. B FIGS. 13A and 13B are cross-sectional views of other embodiments of the lead of the present invention. ll...Lead of lead frame, 12.13 - Main surface of lead. 15.16...Tip of main surface of lead, a.
・Predetermined lead main surface required for wire bonding +1
V^, t...Lead thickness, P...Lead pitch,
20, 21...Lead (tip), :3l...Island of lead frame, 32...Semiconductor straight, 3
3... Lead frame lead, 36... Bonding wire. Figure 1 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
成る樹１指封止型半導体装置において、前ｄ［８リード
フレームのインナーリードの先端部が、その幅方向の断
面では最大幅部分をワイヤボンディングされる主向寄り
に設けた形状にされ、リードピンチが小さく形感すれる
と共に、長手方向の断面では前記ワイヤボンディングさ
れる主面の先端が他の主面の先端よりアイランド側に突
出させた形状にされ、且つ前記アイランドのインナーリ
ードの先端部との対向部は前記アイランドの半導体チッ
プ固着面に対しく・１は垂直な端面を備え、前、ｉ１２
インナーリードの先端部が前記アイランドに近つけられ
たことを特徴とする半導体装置。In a one-finger sealed semiconductor device in which a semiconductor chip is fixed to an island of a lead frame, the tip of the inner lead of the front d[8 lead frame is wire-bonded at the widest part in the cross section in the width direction. It is shaped closer to the main direction, so that the lead pinch is small and the tip of the main surface to which the wire bonding is to be done protrudes toward the island side than the tips of the other main surfaces in the longitudinal cross section. and the portion of the island facing the tip of the inner lead faces the semiconductor chip fixing surface of the island. 1 has a vertical end surface;
A semiconductor device characterized in that a tip of an inner lead is brought close to the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59007074A JPS59150439A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59007074A JPS59150439A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54160826A Division JPS5824020B2 (en) | 1979-12-13 | 1979-12-13 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59150439A true JPS59150439A (en) | 1984-08-28 |
| JPS617736B2 JPS617736B2 (en) | 1986-03-08 |
Family
ID=11655929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59007074A Granted JPS59150439A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59150439A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925927A (en) * | 1996-12-18 | 1999-07-20 | Texas Instruments Incoporated | Reinforced thin lead frames and leads |
| WO2017114564A1 (en) * | 2015-12-29 | 2017-07-06 | Osram Opto Semiconductors Gmbh | Method of etching a metal lead frame |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5287982A (en) * | 1976-01-17 | 1977-07-22 | Sanyo Electric Co Ltd | Resin molding method of semiconductor elements |
-
1984
- 1984-01-20 JP JP59007074A patent/JPS59150439A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5287982A (en) * | 1976-01-17 | 1977-07-22 | Sanyo Electric Co Ltd | Resin molding method of semiconductor elements |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925927A (en) * | 1996-12-18 | 1999-07-20 | Texas Instruments Incoporated | Reinforced thin lead frames and leads |
| WO2017114564A1 (en) * | 2015-12-29 | 2017-07-06 | Osram Opto Semiconductors Gmbh | Method of etching a metal lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS617736B2 (en) | 1986-03-08 |
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