JPS59147545A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To generate an optional signal over a wide frequency region by operating an up-down counter by an output of a rate multiplier in synchronizing with an external signal in a servo system. CONSTITUTION:When an input (x) is preset to the up-down counter CT4, this value is latched 5 and a multiplier of the rate multiplier MP9 is decided. When an external signal in (y) Hz is applied to a terminal 1 in this state, a counter CT7 is reset, ''1'' is outputted to a terminal Q of an FF2, an output of the MP6 is given to a terminal U of the CT4, then ''1'' is generated at a terminal Q' of the FF2 and the output of the MP6 is supplied to a terminal D of the CT4. As a result, in using the contents of the CT7 as an address of an ROM 8, a signal having a waveform of an optional period in synchronizing with the external signal is generated via a D/A converter in response to the digital value of the ROM8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal generation device that generates an arbitrary signal synchronized with an external signal.

For example, a servo analyzer is used to measure the frequency response characteristics of a control system. This device has a function to generate a sine wave, square wave, etc. as a test signal, and this test signal is compared with the output of the measurement target, but this test signal is synchronized with the input of the measurement target. It is used.

Conventionally, PLL (PHL) was used as a hand-held device to obtain a signal synchronized with the input of the measurement target, that is, an external signal.
ASB LOCKED LOOP) is known.

However, this method has the drawback that when the synchronization signal has a low frequency of several Hz or less, the amount of information required for synchronization decreases, making it unstable and requiring a long time to achieve synchronization.

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a synchronization signal generator that can stably generate arbitrary words synchronized with an external signal not only in the low frequency region but also in all frequency regions. The purpose is to

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, numeral 1 connects the μ terminal of input 2 to which an external signal is input. This flip-flop circuit 2 has a Q terminal and a Q terminal connected to a U terminal and a D terminal of an up/down counter 4 via a gate circuit 3L32, respectively. This counter 4 has an M-bit configuration and is configured to receive a preset input (x=mxo).

A rate multiplier 6 is connected to the counter 4f via a latch 5. This rate multiplier 6 is M
It has a bit structure af and is driven by an FHz clock.

The rate multiplier 6 is connected to the gate circuit 32 and the counter 7. This collar R is connected to the input terminal 1 and also to the latch 5.

The counter 7 also has RAM (read only memory) 8.
This ROM 81 is connected to the output terminal 10 via the DA converter 9.

Next, its effect will be explained.

Now, when input x (=mx.) is preset to the up/down counter 4, the output of the counter 4 is latched by the latch 51. Suki, rate multiplier 6
A multiplier is determined and a predetermined output is generated. In this situation,
When an external signal of input terminal 1 jc yHz is given,
As the counter 7 is reset, an 11# output is generated at the Q terminal of the flip-flop circuit 2, and the output of the rate multiplier 6 starts to run up. Also,
At the same time, the output of the rate multiplier 6 is sent to the counter 7. When the counter 7 overflows, the R terminal of the flip-flop circuit 2
1" output is given. Then, an "l" output is generated at the θ terminal of the flip-flop circuit 2, and the output of the rate multiplier 6 is then passed through the gate circuit 32 to the down terminal of the up/down counter 4. This is given to f
From this point on, the counter 4 starts counting down.

Thereafter, when an external signal is applied to input terminal 1, the same operation as described above is repeated. The operational timing in this case is illustrated in FIG. 2. Here, in FIG. 2, (a) is an external signal given with a period of 1/y, (b) is the output of the counter 7, (C) is the output of the Q terminal of the flip-flop circuit 2, and (d) is an up-down signal. The up-count output of the counter 4, and (e) the down-count output of the four counter 4.

In this case, the preset input value of the up/down counter 4 is X, and the output of Carantuff at this time is X.

Hz, the following equation holds true.

However, X=mx,) On the other hand, the number of up pulses per one cycle of the external signal is 1M □ 2 * X X , and the number of down pulses per one cycle of the external signal is . Therefore, the number of pulses that increases or decreases in one cycle is as follows.If the initial value of the up/down counter 4 is set to X, then the following equation holds true after P cycles.

=2M@x The above equation is discrete, but if you think of it as a series or a tiger, you can solve it.

Then, by substituting the equation (11) into the above equation, we get.In other words, the above equation attenuates and finally becomes Y=X.

Now, in order to consider the rate of convergence, we will assume specific numerical values.

That is, Y=2xo, m=100. Good luck with N=10.

Equation (2) is Period = A certain relationship holds true.

As a result, 13) 2) and then X. = 10f (If we set z, P = 3.9 → 4 in the 1-excellence east, P- in the 0.1% convergence
62 → 7 and 0.01% convergence, P = 8.5 → 9, and if the contents of counter 7 at this time are the address of ROM 8, synchronization with the external signal corresponds to the digital value stored in ROM 8. An output signal having an arbitrary periodic waveform (sine wave, square wave, triangular wave, etc.) is generated via the DA converter 9.

In this case, in the above case, the frequency ratio of the external signal and the output signal is 1.
:1, but if a frequency divider is inserted on the output side of the counter 7, a high frequency signal can be obtained, and if the signal is fed back to the flip-flop circuit 2 from the middle of the counter 7, a signal synchronized with a low frequency can be obtained. is obtained.

Therefore, according to the present invention, it is possible to obtain a synchronization signal generating device that can stably generate an arbitrary signal synchronized with an external signal not only in a low frequency region but also in all frequency dispersion regions.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications within the scope without changing the gist.

For example, in the above example, the counter 7, the rate multiplier 6,
Although the up/down counter 4 has been described as a binary counter, it is of course not limited to this.

Further, in order to synchronize with an external signal in a short period of time, it is sufficient to measure the frequency of the external signal, perform a reciprocal calculation, and provide this value as the input X of the up/down counter 4.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing one embodiment of this invention □
, FIG. 2 is a time chart for explaining the same embodiment.

Claims (2)

[Claims] (1) An up/down counter, a rate multiplier whose multiplier is determined according to the contents of the up/down counter, a counter that counts the output of this rate multiplier, and a counter that counts the output of the rate multiplier in synchronization with an external signal. A means for causing the up/down counter to count up at the output and waiting for an overflow of the counter to cause the output of the rate multiplier to count down, and an arbitrary means depending on the contents of the counter. 1. A synchronization signal generation device comprising: means for generating a periodic waveform output. (2) The synchronization signal generating device according to claim 1, further comprising means for latching the contents of the up/down counter.