JPS5914675A - thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a membrane transistor.

Conventionally, thin film transistors having a staggered electrode structure shown in FIGS. 1 and 2 and those having a coplanar electrode structure shown in FIGS. 3, 4, and 5 are known. In each figure, 1 is an insulating substrate, 2 is a gate electrode, 3 is an insulator layer, 4 is a thin film semiconductor layer, 5 is a source electrode, and 6 is a drain electrode. The output characteristics of thin film transistors vary greatly depending on the distance between the source and drain, that is, the channel length. In particular, in order to increase the maximum operating speed in terms of operating characteristics, it is preferable to shorten the channel length as much as possible. However, in the method of using a vapor deposition mask or the method of using photoetching to form the distance between the source and drain, the channel length is limited to about several μm due to manufacturing constraints.

On the other hand, the mobility of a thin film semiconductor layer is smaller than that of a bulk semiconductor, and particularly when formed at a low temperature, the mobility is extremely reduced. For example, an amorphous silicon film formed by glow discharge decomposition of silane at a substrate temperature of 300°C, or a polycrystalline silicon film formed by molecular beam growth at a substrate temperature of 500°C, can only obtain a small mobility of several cR/vo or less. Not yet. Therefore, Figures 1 to 5
In a thin film transistor having a staggered or coplanar electrode structure as shown in the figure, the channel length can be reduced to only a few micrometers, so the maximum operating speed can only be as low as several MH2 or less.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor which improves the above-mentioned drawbacks and has a high maximum operating speed.

According to the present invention, a two-layer structure consisting of at least a thin film semiconductor layer and an insulating layer is provided on an insulating substrate, and a sum electrode and a drain electrode are provided sandwiching the thin film semiconductor layer of the two-layer structure. There is obtained a thin film transistor characterized in that a gate electrode is provided at a position facing the source electrode or the drain electrode with the insulating layer sandwiched therebetween.

In the thin film transistor of the present invention, as shown in FIGS. 6 and 7, the channel layer between the source and drain electrodes facing each other with the thin film semiconductor 4 in between is insulated from either the source electrode 5 or the drain electrode 6. Since the channel is formed by gate electrodes facing each other with the body layer in between, the channel length is equal to the thickness of the thin film semiconductor. The thickness of the thin film semiconductor can be accurately controlled from about several tens of meters, and the vertical extension of the channel layer in the thin film semiconductor when voltage is applied to the gate electrode is about several hundred nm. Therefore, the channel length can be shortened to several tens of minutes compared to a thin film transistor formed by photoetching or the like. Since the maximum operating speed in terms of dynamic characteristics is inversely proportional to the square of the channel length, the thin film transistor of the present invention can increase the maximum operating speed several hundred times as compared to conventional thin film transistors. Furthermore, since the source-drain current is inversely proportional to the channel length, the size of the thin-film transistor can be reduced to about a few tenths of the size, even though the source-drain current is the same as that of a conventional thin-film transistor.

The present invention will be explained below with reference to examples. In the examples, an amorphous silicon film made by glow discharge decomposition of silane was used as the thin film semiconductor layer, but other semiconductors that can be made into thin films such as CdS, edge, etc.
Needless to say, semiconductors such as 9Te, etc., semiconductors such as Ge, and thin film silicon semiconductors produced by other manufacturing methods, such as polycrystalline silicon thin films produced by molecular beam growth or polycrystalline silicon films produced by laser annealing, can also be used.

Example 1 As shown in FIG. 6, a gate electrode 2 was formed on an insulating substrate 1, and a mixed gas containing 20% hydrogen-based silane, ammonia, and nitrogen was flowed over the substrate at 200 c8/min at a pressure of 0.3 ton. High frequency power 20W 1 substrate temperature 300
After forming a silicon nitride film at 11°C, a source and an electrode 5 were formed so as not to cover a part of the gate electrode 2, and then a hydrogen-based 20% silane film was further formed thereon.

Amorphous silicon was formed at a flow rate of 100 α min, a pressure Q of 2 tons, a high frequency power of 10 W, and a substrate temperature of 300° C. A drain electrode 6 was formed on this semiconductor film so as to cover the gate electrode 2 not covered by the source electrode 5 to form a thin film transistor. Silicon nitride film thickness 0
．． The thickness of the amorphous silicon MiE was 3 μm, o, s μm, the channel length was 0.5 μm, and the channel width was 50 μm. The thin film transistor manufactured in this way has a gate voltage of 10v1 and a drain voltage of 1Ov in the on state.
050α or less, gate voltage Ov1□ drain voltage 10V
Maximum operating speed of 1011QGIrL or higher in the off state of 1
It was more than 00MH2. These values were not only sufficient for, for example, a switching element of a liquid crystal, but also a value sufficient for a drive circuit element when the switching element is driven by a television signal. This is because the thin film transistor of the present invention has a source electrode 5 and a drain electrode 6 facing each other across a thin film semiconductor layer 4, and a gate electrode 2 facing each other across a source electrode 5 and an insulator layer 3. This is thought to be due to the fact that the channel length is determined by the semiconductor film thickness, so the channel length can be shortened.

Example 2 As shown in FIG. 7, a so-sumi sharpener 5 was formed on an insulating substrate 1, and 10% argon-based silane was flowed on the substrate at a flow rate of 100cc7ntin, a pressure of 0.3ton, high frequency power of 10W, a substrate temperature of 300℃. Amorphous silicon was formed at ℃. Next, a drain electrode 6 is formed so as not to cover a part of the source electrode 5, and the semiconductor layer is further treated with oxygen plasma. Then, in the same vacuum system, a mixed gas containing argon base 10 silane and argon base 10% oxygen is heated.
A silicon oxide film was formed at a flow rate of 0.00 cc/min, a pressure of 0.110 n, high frequency power of 20 W, and a substrate temperature of 300°C. A gate electrode 2 was formed on this insulator film so as to cover the source electrode 5 not covered by the drain electrode 6, thereby forming a thin film transistor. Silicon oxide film thickness is 0.3μIn
The amorphous silicon film thickness was 0.5 μm, the channel length was 0.5 μm, and the channel width was 50 μm. The thin film transistor manufactured in this manner also had good characteristics equivalent to those of Example 1. This seems to be due to the same reason as in Example 1.

As described above, according to the thin film transistor of the present invention, it is possible to increase the maximum operating speed in terms of dynamic characteristics, and at the same time, it is possible to reduce the size of the element.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views of conventional staggered electrode structure thin film transistors, Figures 3, 4, and 5 are cross-sectional views of conventional coplanar electrode structure thin film transistors, and Figures 6 and 7. The figure is a cross-sectional view of the thin film transistor of the present invention. In the figure, 1 is an insulating substrate, 2 is a gate electrode, 3 is an insulator layer, 4 is a thin film semiconductor layer, 5 is a source electrode, and 6 is a drain electrode. Figure 7 Figure 4: 77 Chairs Figure 1'

Claims (1)

[Claims] It has a two-layer structure consisting of at least a thin film semiconductor layer and an insulating layer on an insulating substrate, and a source electrode and a drain electrode are provided sandwiching the thin film semiconductor layer of the two-layer structure, and an armpit source electrode or a drain electrode. A thin film transistor characterized in that a gate electrode is provided at a position opposite to the insulating layer with the insulating layer interposed therebetween.