JPS59144932U - Blocking oscillation circuit - Google Patents
Blocking oscillation circuitInfo
- Publication number
- JPS59144932U JPS59144932U JP3925983U JP3925983U JPS59144932U JP S59144932 U JPS59144932 U JP S59144932U JP 3925983 U JP3925983 U JP 3925983U JP 3925983 U JP3925983 U JP 3925983U JP S59144932 U JPS59144932 U JP S59144932U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation circuit
- blocking oscillation
- resistor
- blocking
- midpoint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のブロッキング発振回路の回路図、第2図
は第1図におけるブロッキング発振回路の電源電圧の変
化に伴なう発振周波数の変化を示すグラフである。第3
図は他の従来のブロッキング発振回路の回路図である。
第4図は本考案に係るブロッキング発振回路の回路図、
第5図は第4図におけるブロッキング発振回路の電源電
圧の変化に伴なう発振周波数の変化を示すグラフである
。
20・・・電源入力端子、21・・・第1の抵抗、22
・・・第2の抵抗、23・・・第3の抵抗、24・・・
ブロッキング発振用の、トランジスタ、25・・・ツェ
ナーダイオード、33・・・出力端子。FIG. 1 is a circuit diagram of a conventional blocking oscillation circuit, and FIG. 2 is a graph showing changes in oscillation frequency with changes in power supply voltage of the blocking oscillation circuit in FIG. Third
The figure is a circuit diagram of another conventional blocking oscillation circuit. FIG. 4 is a circuit diagram of a blocking oscillation circuit according to the present invention,
FIG. 5 is a graph showing changes in oscillation frequency with changes in power supply voltage of the blocking oscillation circuit in FIG. 4. 20... Power input terminal, 21... First resistor, 22
...Second resistance, 23...Third resistance, 24...
Transistor, 25... Zener diode, 33... Output terminal for blocking oscillation.
Claims (1)
れた電源入力端子と接地との間に第1ないし第3の抵抗
を直列接続し、第1の抵抗と第2の抵抗の接続中点をツ
ェナダイオードを介して接地するとともに、第2の抵抗
と第3の抵抗との接続中点を上記トランジスタのベース
に接続したことを特徴とするブロッキング発振回路。First to third resistors are connected in series between the power input terminal to which the collector of the blocking oscillation transistor is connected and the ground, and the midpoint of the connection between the first resistor and the second resistor is connected through a Zener diode. A blocking oscillation circuit characterized in that the second resistor and the third resistor are grounded, and a midpoint between the second and third resistors is connected to the base of the transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3925983U JPS59144932U (en) | 1983-03-18 | 1983-03-18 | Blocking oscillation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3925983U JPS59144932U (en) | 1983-03-18 | 1983-03-18 | Blocking oscillation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59144932U true JPS59144932U (en) | 1984-09-27 |
Family
ID=30169911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3925983U Pending JPS59144932U (en) | 1983-03-18 | 1983-03-18 | Blocking oscillation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59144932U (en) |
-
1983
- 1983-03-18 JP JP3925983U patent/JPS59144932U/en active Pending
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