JPS5914356A - Gate controller for gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To safely control On or OFF a GTO by detecting the voltage of a snubber condenser in a snubber circuit and stopping the gate current when the voltage becomes a reference voltage or lower. CONSTITUTION:When a GTO 10 is OFF state, a snubber condenser 21 is charged to the prescribed voltage. When a signal from a gate trigger signal generator 80 is supplied to an NAND circuit 61, the GTO 10 starts turning on, and the charging voltage of the condenser 21 decreases. When the voltage of the condenser 21 becomes the reference voltage or lower, a Zener diode 42 conducts, and a field effect transistor 51 conducts. In this manner, the output of the NAND circuit 61 becomes high level, a field effect transistor becomes OFF, and the gate current of the GTO 10 becomes OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate control device for a semiconductor switching element, and particularly to a gate control device for a gate turn-off thyristor.

A gate turn-off thyristor is used as a switching element in a control device that controls AC power or DC power.

Among such control devices, the on-gate current of the gate turn-off thyristor during an inductive load is supplied for the entire period during which the corresponding main switching element is to be turned on. There is.

This is because when the load has a lagging power factor, the anode voltage reverses from negative to positive with a delay after the rise of the output pulse of the gate trigger pulse signal generation, so the gate turn-off thyristor is turned on with a narrow time width of the ON gate pulse. This was because there were cases where it was not possible to arc.

In this method of applying an on-gate pulse over the entire on period, the electric energy supplied from the gate driver becomes considerably large, and the gate driver also has to be large.

In order to solve such problems, an on-gate signal supply system as shown in FIG. 1 has been proposed. That is, in FIG. 1, S1 is the anode voltage of the gate turn-off thyristor, S2 is the output signal of the gate trigger signal generator, and S3 is the gate current waveform applied to the gate turn-off thyristor.

As shown in FIG. 1, the reference voltage Vref is set to a certain value higher than the steady-state on-voltage V7 of the gate turn-off thyristor.The output signal S2 of the gate trigger signal generator is applied to the gate driver. Only during the period from time to to time t1 when the anode voltage of the gate turn-off thyristor decreases and becomes equal to the reference voltage Vref,
The amplified gate current S3 is supplied to the corresponding gate turn-off thyristor, thereby making it possible to reduce the electrical energy supplied from the gate driver. However, this method has the following drawbacks and has not been put to practical use.

In gate turn-off thyristors for large currents, the cathode electrode section is generally divided into a number of islands, and the on-current=on-voltage characteristic of the gate turn-off thyristors is as shown in curve 1 in FIG. ．． As shown in Figure 12, as the on-state current (I) increases, the on-state voltage M increases. Therefore, if you try to achieve the desired purpose even in a large current region, the reference voltage Vref will change according to the temperature characteristics shown in Fig. 2. curve 1
．． , 12, it must be set higher than the VTI. However, if the reference voltage vref is set high, the element may be destroyed due to the following reasons (.

In other words, in the case of IT2, where the anode current at turn-on (before t+ in Figure 1) is relatively low, the anode is The voltage is higher than vT2, but the reference voltage V
will be lower than the gate ref.

The current disappears at time t1.

Therefore, there is a very low possibility that the cathode islands that were not turned on before t1 will be turned on in the period after this.

Furthermore, as the anode current increases in this state, the temperature of the cathode islands in the on state rises, and the temperature difference between them and the cathode islands in the off state increases.

As shown in FIG. 2, the on-voltage of the gate turn-off thyristor lowers the on-voltage of the cathode island where the junction temperature is high, making it even more difficult for the current to spread to the cathode island that is in the off state.

Therefore, if a negative pulse is applied to the gate in this state, the power loss density during the falling period of the island portion of the cathode that is currently in the on state becomes extremely high, and there is a high risk of destroying the device.

Therefore, narrowing the on-gate current pulse width of the gate turn-off thyristor by the method shown in FIG. 1 has a problem with the safe operation of the device, and cannot be put to practical use.

The present invention obviates the above-mentioned drawbacks and its purpose is to:
To provide a gate control device that can turn on a gate turn-off thyristor or ensure its on state, can significantly reduce electric energy supplied from the outside, and can operate safely.

A gate control device for a gate turn-off thyristor according to an embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

In FIG. 3, 10 is a controlled switching element. However, this is a gate turn-off thyristor (hereinafter referred to as GTO).

20 is a snubber circuit added to GTOlo.

30 is a control power supply circuit having a DC power supply 31. 4° is G
This is a detection circuit that detects the capacitor voltage of the TOIO snubber circuit 2o.

Reference numeral 60 represents a logic circuit for generating the detection symbol of the detection circuit 40 and a trigger signal from the gate trigger signal generator 80, and reference numeral 70 represents a gate drive circuit that turns on and off the gate current of the GTOIO in accordance with the output signal of the logic circuit 60.

The snubber circuit 20 includes a snubber capacitor 21 and a resistor 22.
, a diode 23.

Diode 24 is a freewheeling diode.

The snubber capacitor 21 is connected to the GTO1 via the discharge resistor 22.
A diode 23 is connected between the anode and cathode of
is connected in parallel to the resistor 22 so that its anode is on the anode side of GTOIO.

Freewheeling diode 24 is connected anti-parallel to GTOIO.

The snubber capacitor voltage detection circuit 40 has the following configuration. That is, it has a resistor 41, a zener diode 42, and a reverse current blocking diode 43 that are connected in series with each other, one end of the resistor 41 is connected to the positive terminal of the DC power supply 31, and the cathode side of the diode 43 is connected to the positive terminal of the DC power supply 31. It is connected between the connection point of the snubber capacitor 21 and the resistor 22.

The gate electrode of the first field effect transistor 51 is connected to the connection point between the Zener diode 42 and the resistor 41, the source electrode is connected to the positive electrode of the power source 31, and the drain is connected to the negative electrode of the power source via the resistor 52, respectively. field effect transistor 5
A signal inversion circuit 5 is connected to the connection point between the drain electrode 1 and the resistor 52.
30 input side is connected. With the snubber capacitor voltage detection circuit 40 configured in this manner, the reference voltage Vref shown in FIG. It can be varied by selecting an appropriate Zener voltage.

The logic circuit 60 is composed of a NAND circuit 61, and one input terminal of the NAND circuit 61 is connected to the output terminal of the signal inversion circuit 53. The other input terminal is connected to the output side of the gate trigger signal generator.

The gate drive circuit 70 is a second field effect transistor 71
and resistors 62 and 72, the gate electrode of the transistor 71 is connected to the output terminal of the NAND circuit 61 and the positive electrode of the power supply 31 via the resistor 62, and the drain electrode is connected to the gate electrode of the GTOIO via the resistor 72. has been done.

Next, the operation of the circuit shown in FIG. 3 will be explained. In the gate control device having the above configuration, when the GTOIO is in the OFF state, the snubber capacitor 21 is charged to a predetermined voltage as shown by the curve t3 in FIG. 4.

Now, when the signal from the gate trigger signal generator 80 is supplied to the other input side of the NAND circuit 61 at the time to, since one input side is a high level input as described later, this NAND circuit 61 The output signal becomes low level, the field effect transistor 71 is turned on, and an on-gate current is supplied to the gate of G'I'OIO.

As a result, the GTO 10 begins to turn on, the anode current begins to flow, and the anode voltage (VA) increases to the fourth
It begins to descend as shown in the figure. At this time, the charge of the snubber capacitor 21 is discharged at the anode of the resistor 22°GTOIO and the colored loop of the snubber capacitor 21, and the charging voltage V8 of the snubber capacitor 21 is as shown by the curve t4 in FIG. Quantitative value C
8 and the resistance value R8 of the resistor 22.

Difference voltage between control power supply voltage v1 and snubber capacitor vs (
v, -Vs) is a predetermined value, that is, the Zener diode 42
When vs becomes smaller than the zener voltage VZ, the zener diode 42 becomes conductive. A reference voltage (Vref, ) for turning off the gate current to be applied to the GTOIO is set by the zener voltage Vz at this time.

In addition, Vref is VZ of Zener diode and diode 4
The voltage is the sum of the forward voltage drop of 3. Therefore, when the voltage Vs of the snubber capacitor 21 becomes lower than the reference voltage "ref," the zener diode 42 becomes conductive and the resistor 41
The voltage drop is the threshold voltage V of the field effect transistor 51. 5(ih1 or more), the first field effect transistor 51 becomes conductive.

When the first field effect transistor 51 becomes conductive, the resistor 5
The voltage at the connection point J2 of 2 increases to a high level as shown by curve t5 in FIG. 4, and the output of the signal inversion circuit 53 becomes a low level as shown by curve t and 6 in the same figure.

Therefore, when the trigger signal from the gate trigger signal generator 80 is applied to the other input side of the NAND circuit 61 as shown by the curve t7, the output of the NAND circuit 61 becomes high level as shown by the curve t8b. The second field effect transistor 71 is turned off. This allows the curve t
As shown in 9, the gate current of GTOlo is turned off.

In the conventional method shown in Fig. 1, the anode voltage VA is detected,
GTO is activated at time t1 when the reference voltage Vr e f becomes below.
Since the current supplied to the gate of the snubber capacitor 21 is turned off, it has the above-mentioned drawback and cannot be put to practical use. However, according to the present invention, the voltage Vs of the snubber capacitor 21 is detected, and it is set to the reference voltage Vref, or lower. In order to stop the current supplied to the gate of the GTOIO at the time t2, the timing of stopping the gate current can be delayed by Δt'' (t2 J) as shown in FIG.

Therefore, the conditions necessary for the anode current of the GTOIO to rise to a sufficiently high value and to turn on almost all of the separate cathode emitters can be created.

Further, the delay time Δt can be arbitrarily selected by appropriately selecting the resistance value R8 of the discharge resistor 22 of the snubber circuit 20. Therefore, the GTOIO can be completely turned on and off, and the electrical energy to be supplied to the gate of the GTOIO can be significantly reduced compared to the method of supplying gate current throughout the entire on period of the GTO. As a result, the gate driver can be significantly downsized.

Figure 5 shows a single-phase bridge inverter device using GTOs, including GTOs 10a, 10b, 10c and 1.
0d, and each of these GTOs has a snubber circuit 2.
0a, 20b, 20c and 20d are provided.

Also, in Fig. 5, 21 a + 21 b + 2
1c and 21d are snubber capacitors, 22
a, '22b.

22c and 22d are discharge resistors, 23 a +
23 b +23c and 23d are diodes, 24
a, 24b, 24c and 24d are each flywheeling diodes.

Further, 90 is a DC power supply, and 100 is a load.

FIGS. 6 and 7 show operating waveforms when the gate control device of the present invention is applied to the inverter device shown in FIG. 5.

That is, FIG. 6 shows the operating characteristics when the inverter is started or when the load power factor is relatively good (when the resistance component is large).

When the signal from the gate trigger signal generator is applied to the gate drive circuit, it is amplified therein and supplied to the gate of the GTO. This causes the GTO to begin to turn on, the anode voltage to drop as shown, and the anode current to begin flowing. The voltage of the snubber capacitor is the reference voltage Vrof.
In order to stop the current supplied to the gate of the GTO at the time (t2) when , or less, the anode current rises to a sufficiently high value as shown in the figure by delaying the stop time of the gate current by the time Δ. At this time, the discharge current of the snubber capacitor is expressed by the area surrounded by the curve t10.
It becomes iA. This discharge current causes the voltage Vs of the snubber capacitor to drop to the reference voltage Vref, and the same effects as in the previous embodiment can be obtained.

Further, FIG. 7 shows the operating characteristics of the inverter when the load 100 has a lagging power factor, and in this case as well, the same effect as shown in FIG. 6 can be obtained.

Incidentally, the time t1 shown in FIGS. 6 and 7 is the stop time of the gate current according to the conventional method shown in FIG.

As is clear from the above description, according to the present invention, the voltage of the snubber capacitor in the snubber circuit attached to the gate turn-off thyristor as a protection circuit is detected, and when the voltage falls below the reference voltage, the gate current is stopped. As a result, the gate turn-off thyristor can be safely controlled on and off.Furthermore, according to the present invention, the time delay between the drop in the anode voltage of the gate turn-off thyristor and the drop in the snubber capacitor voltage is utilized. This has excellent effects both technically and practically, such as ensuring the turn-off and latency of the gate turn-off thyristor and obtaining a high-performance and highly reliable gate control device. has.

Further, even if the FET and FET2 in the figure are replaced with bipolar transistors, the same functions and effects as in the above embodiment can be obtained.

[Brief explanation of the drawing]

Fig. 1 is an operating characteristic diagram of a conventional gate turn-off thyristor according to a gate control method, Fig. 2 is a characteristic diagram of on-voltage and on-current depending on temperature of the gate turn-off thyristor, and Fig. 3 is a gate turn-off according to an embodiment of the present invention. An electric circuit diagram of a thyristor gate control device, FIG. 4 is an operating characteristic diagram of the gate control device of FIG. 3, FIG. 5 is an electric circuit diagram of an inverter using a gate turn-off thyristor, and FIGS. 6 and 7 are 6A and 6B are operational characteristic diagrams when the gate control device of the present invention is used in the inverter shown in FIG. 5, respectively. DESCRIPTION OF SYMBOLS 10... Gateter/off thyristor, 20... Snubber circuit, 21... Snubber capacitor, 22... Discharge resistor, 30... Power supply circuit, 31... DC power supply,
40... Snubber capacitor voltage detection circuit, 6
0...Logic circuit, 70...Gate drive circuit, 80.
・Gate trigger signal generator application agent Patent attorney Gobe Kikuchi Figure 2 Figure 2 Voltage

Claims (1)

[Claims] a first means for detecting the voltage of a snubber capacitor connected in parallel with the gate turn-off thyristor and outputting a binary signal when the capacitor voltage becomes below a reference voltage; and an output from the gate trigger signal generation circuit. and the output from the first means;
a third means for turning on and off a switching element connected to the gate of the gate turn-off risk by the output of the means; A gate control device for a gate turn-off thyristor, characterized in that the gate current flowing through the gate of the gate is stopped.