JPS59132212A - Operational amplifier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to operational amplifiers, and more particularly to the use of various components forming single-channel circuits such as encoder-decoder (CODEC) subscriber loop (sLIC) twin-interface circuits. Concerning a suitable operational amplifier.

- BACKGROUND ART In such circuits that are extremely sensitive to variations in the energy source (especially in the absence of a feedback loop or in cases where the loop has only a small degree of feedback), the effects of variations in the energy source on the useful output signal are Differential amplifier techniques can be used that completely cancel out the effect, since this signal is the difference between the two signals sent on a line that is not at ground potential.

However, this technique cannot be used for the final output signal of most of the circuits described above. This is because this signal often has to be transmitted asymmetrically. This is the case, for example, in the subscriber set (circuit 5LIC).

In the past in the field of telecommunications, filter circuits were used to remove the effects of energy source variations on asymmetric differential output stages, but this technology has become more expensive in advanced technology. , the frequencies used are increasing due to the complexity of filters.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a C
In a MOS operational amplifier, the spectrum of energy source fluctuations is completely eliminated or at least reduced to an acceptable extent.

Another object of the invention is an operational amplifier with symmetrical inputs and asymmetrical outputs, the symmetrical amplifier chain having two differential inputs and two differential outputs, one of whose outputs is the asymmetrical output of the circuit. a symmetrical amplifier chain comprising said symmetrical amplifier chain; a summing circuit connected to the output of the amplifier chain; and a current source for supplying current to at least a portion of the amplifier chain; , a feedback loop for controlling said current sources in opposite phase to the sum of fluctuations appearing at the output of the amplifier chain.

Because of these features, this circuit provides a feedback loop that allows variations in the common mode output signal due to the power source to be fed back to the input of the amplifier chain without affecting the differential signal that is transmitted to the output terminals without feedback. It's breaking down. Feedback loop is 0
Consisting of transistors forming part of the M08 circuit, this solution is inexpensive and 1f3. Appropriately suppress transient phenomena introduced from the source.

Other features and advantages of the invention will become apparent from the following description with reference to the drawings, which are given by way of example only.

FIG. 1 shows a simplified schematic diagram of an amplifier according to the invention. Amplifier stage 1 comprises two amplifier devices 7 constituting a second amplifier stage 9 of the circuit.
, 8 and have symmetrical outputs on the ground wires 5, 6. One of the amplifiers i 7 is adapted to generate a useful output signal on terminal 10 taken to reference lead 17.

Terminal 10 is also connected to a summing circuit 12 which is connected to an output lead 13 of second amplifier device 8 . The output of the summing circuit 12 is connected to one input of a differential amplifier 15 with a uniform gain, the other input of which is connected to a reference voltage source 17, which in the illustrated example is ground.

The output 18 of the amplifier 15 is connected to an adjustable current source 19 which supplies the first amplifier stage 1 with a supply voltage present between the terminals DD and S8 and σ.

It is generally known that differential circuits are not affected by fluctuations in the supply voltage because the fluctuations are applied to the two differential lines of the circuit with the same phase and amplitude. In the illustrated example, these variations do not prevent proper transmission of the differential signal through the circuit before reaching the summing circuit 12. This is not the case with respect to terminal 10, which together with terminal 17 constitutes the asymmetric output of the circuit. fruit[
Unfortunately, variations in the supply voltage with respect to ground in this case are substantial and superimposed on the useful output signal in the absence of filters or other special precautions.

According to the invention, the signals appearing at the outputs 10.13 are summed in a summing circuit 12 and applied to an amplifier 15 which inverts the phase of the fluctuations and amplifies them with uniform gain.

The signal representing the fluctuations is compared to a reference signal on lead 16 and the error signal is applied as a regulation signal to the sub-current source 19 so that the fluctuations introduced by voltages vdd and vss are compensated for in the common mode output. .

FIG. 2 illustrates a preferred embodiment of an amplifier according to the present invention. It is constructed in 0MO8 technology and all circuits of FIG.
0.21, whose r-ts are each symmetrical input terminal 2, 3
connected to. The source-drain path is connected in series with two further transistors 22, 23, which constitute the two amplifier transistors 20.degree. 210 load resistance and serve as current sources. The outputs 5, 6 of this amplifier stage 1 appear on the one hand at the junction between transistors 20.22 and on the other hand at the junction between transistors 21.23, respectively.

The amplifier ff7.8 includes an amplifier transistor 24°25 whose gate is connected to the outputs 5, 6 and whose source
The drain path constitutes a load resistance and functions as a current source2
The transistors 26 and 27 are connected in series. The output 10 of the circuit is the junction between transistors 25, 27, while the connection 13 with the circuit 12 is the junction between transistors 24, 26. Frequency correction circuits 28.19 are associated with amplifier transistors 24.25.

The summing circuit 12 includes two summing resistors 30.31 connected to the terminal 13.10 and shunted by a capacitor 32.33.
The capacitor acts as a compensator for the feedback loop of the operational amplifier. The output of the summing circuit is the first output 14 of the uniform gain amplifier 15, i.e. the pt of the transistor 34.
This transistor 34 is connected to another transistor 35, and the r- of this transistor 35 is connected to
1- (input 16) is connected to a reference source 17 (ground in the illustrated example). The sources of transistors 34 and 35 are
It is commonly connected to a transistor 36 that constitutes a current source of the amplifier 15. The source-drain path of each of the transistors 34 and 35 is connected to the transistor 3 constituting a load resistance.
7.38 respectively.

The output signal of amplifier 15 appearing at the gate of transistor 37 is connected to current source 19 consisting of transistor 39.
and its source-drain path is connected to the first amplifier stage 1.
is connected to supply current to the transistors in this stage.

Biasing transistors 40-43 perform biasing of the dates of all current sources.

FIG. 6 shows a modification of the first amplifier stage 1.

In order to reduce the effect of capacitance disparities at the inputs 2, 3 of this amplifier stage, the amplifier and load transistors 20, 22 and 2
1. Installed in series with 23 and all with constant flow source 1
Also included is a cascade of transistors 44, 45 biased by a group of six transistors 46-48 mounted in series between 9 and the line vss.

The invention thus provides a symmetric/asymmetric operational amplifier in which transients from the power source are virtually eliminated at the output.

This amplifier has a very high common mode rejection ratio (CMRR)
It has excellent characteristics that produce a high power supply rejection ratio (PSRR).

The amplifier according to the invention made by the inventor cures the following characteristics, the values of which are given by way of example only.

Power supply +5. -5V Load 20 p, F' Humidity temperature 27°C Gain 1% 10 Hz--78dB20
'OHz ---= 20 dB uniform gain band
2.5MHz output signal output - peak voltage range
-4,9 to 6.6V common mode range -6
,2 to 2.9■CMRR10Hz--118dB 200Hz-=-41dB VddC',) PSRR10Hz ""'・116d
B200 Hz ----54dB vs8 PSRR10Hz-114dB200Hz-
= -42aB Start-up time 1.8 microseconds/0.1% of 1 volt step slope ratio in 1 volt step 3.2 V/microsecond total harmonic distortion (sine wave 3 KHz/6V peak-to-peak ) [1
,008% power consumption 1.5mw

[Brief explanation of drawings]

FIG. 1 is a simplified schematic diagram of an operational amplifier according to the invention;
FIG. 2 is a detailed schematic diagram of this amplifier, and FIG. M6 is a diagram showing a modification of the input stage of the amplifier shown in FIG. Explanation of symbols 1...First amplification stage, 7, 8...Amplification device, 9...
2nd amplification stage, 12... Addition circuit, 15... Error amplifier, 17... Reference voltage source, 19... Current source. Agent Akira Asamura Procedural amendment (method) February 13, 1980 To the Commissioner of the Patent Office, Special Application No. 201890 of 1988 2, Title of invention 3, Relationship with the case of the person making the amendment Special 2'1 Applicant Address Name 1 Kissas Instruments Inc. (Name) 4. Agent 5. Date of amendment order January 31, 1980

Claims (7)

[Claims] (1) In an operational amplifier having symmetrical inputs and asymmetrical outputs, a symmetrical amplifier chain having two differential inputs and two differential outputs, one of the outputs of which constitutes the asymmetrical output of the circuit. an adder circuit connected to the output of the amplifier chain; a current source supplying current to at least a portion of the amplifier chain; and a current source connected between the adder circuit and the current source and connected to the output of the amplifier chain. An operational amplifier having a symmetrical input and an asymmetrical output, characterized in that it comprises a feedback loop that controls the power supply in opposite phase with respect to the sum of fluctuations that appear. (2) 11? The amplifier of claim 1, wherein the feedback loop includes two error amplifiers connected respectively to the output of the summing circuit and the reference voltage source;
An amplifier characterized in that an output of the error amplifier is connected to the current source. (3) The amplifier according to any one of claims 1 to 2, wherein the amplifier chain includes a first differential stage which is also supplied with current from the power supply. a second stage having two different amplifying devices, one of which includes an output connected to an output terminal of the circuit and said summing circuit, while the other of said devices is directly connected to said summing circuit; and said second stage including an output connected thereto. (4) An amplifier according to claim 1-11(6), wherein the first amplifier stage includes two differential amplifier transistors each connected in series via its source-drain path; An amplifier characterized in that a source-drain path of the transistor constitutes a load resistance and operates as a current source, and both value string circuits of the transistor are connected to the controlled current source. (5) An amplifier according to claim 4, characterized in that the first amplifier stage also includes in each differential section a cascade of transistors biased by a transistor chain connected to the current source. amplifier. (6) In the amplifier according to any one of claims 1 to 5, the error amplifier includes two transistors connected in series to two transistors constituting a load resistance.
an amplifier characterized in that it includes several differential transistors, these components being commonly supplied with current from other current sources. (7) Scope of Patent iJ'J In the amplifier according to any one of paragraphs 1 to 6, each of the adder circuits is connected on one side to the output of the amplifier chain and on the other side to the output of the error amplifier. An amplifier characterized in that it includes two resistors commonly connected to corresponding inputs.