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JPS59128828A - Inverter circuit - Google Patents

Inverter circuit

Info

Publication number
JPS59128828A
JPS59128828A JP58003650A JP365083A JPS59128828A JP S59128828 A JPS59128828 A JP S59128828A JP 58003650 A JP58003650 A JP 58003650A JP 365083 A JP365083 A JP 365083A JP S59128828 A JPS59128828 A JP S59128828A
Authority
JP
Japan
Prior art keywords
voltage
channel
inverter circuit
vdd
threshold voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58003650A
Other languages
Japanese (ja)
Inventor
Katsuhiko Sudo
克彦 須藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP58003650A priority Critical patent/JPS59128828A/en
Publication of JPS59128828A publication Critical patent/JPS59128828A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H03K19/09482—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors using a combination of enhancement and depletion transistors
    • H03K19/09485—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To eliminate the need for a level shift circuit by adopting depletion type to a P channel IGFET and enhancement type to an N channel IGFET to bring a threshold voltage of the N channel IGFET into a power supply voltage or over. CONSTITUTION:When an input voltage is larger than a threshold voltage Vtn of the N channel IGFET12, the N channel IGFET12 is conductive and the P channel IGFET11 is cut off. Thus, when the input voltage VIN is smaller than VDD+ Vtp where VDD is the power supply voltage and Vtp is the threshold voltage of the FET11, the FET11 is conductive and the FET12 is cut off. Then, an output voltage Vout goes to the voltage VDD level. Thus, in the input/output characteristic of the inverter circuit, the output goes a high potential when the input voltage VIN is VDD+Vtp or below, and goes to a low voltage when the input voltage is the Vtn or over, then the threshold voltage Vt of the inverter circuit is set between the VDD+Vtp and Vtn depending on the impedance ratio when both the FET11, 12 are cut off.

Description

【発明の詳細な説明】 （イ）技術分野 本発明はコンプリメンタリ−ＩＧ　　ＦＥＴで構成され
るインバータ回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field The present invention relates to an improvement in an inverter circuit composed of complementary IG FETs.

（ロ）背景技術 従来のコンプリメンタリ−ＩＧ　　ＦＥＴで構成される
インバータ回路を第１図に示す。（１）はＰチャンネル
ＩＧ　　ＦＥＴであり、（２）はＮチャンネルＩＧ　　
ＦＥＴであり、両ＩＧ　　ＦＥＴ（１）（２）は共にエ
ンハンスメントタイプである。夫々のＩＧ　　ＦＥ　Ｔ
　（１）（２）のスレッシュホールド電圧なＶｔｐ、　
Ｖｔｎとすると、第２図に示す入出力特性が得られる。(B) Background Art FIG. 1 shows an inverter circuit composed of conventional complementary IG FETs. (1) is a P-channel IG FET, and (2) is an N-channel IG FET.
Both IG FETs (1) and (2) are enhancement type. Each IG FET
(1) The threshold voltage of (2) Vtp,
Vtn, the input/output characteristics shown in FIG. 2 are obtained.

インバータ回路の電源電圧をｖＤＤｓ　Ｖ８Ｂとし、■
□を接地電位として説明すると、入力電圧Ｖ、。The power supply voltage of the inverter circuit is vDDs V8B, and ■
If we assume that □ is the ground potential, then the input voltage is V.

がＶｔｎより大きい場合にはＮチャンネルＩＧ　　ＦＥ
　Ｔ　（２１が導通し、入力電圧Ｖ、Ｈが■。−Ｉ　Ｖ
ｔｐ　１より小さい場合にはＰチャンネルＩＧ　　ＦＥ
Ｔ（１）が導通する。従ってインバータ回路はＶｔｎと
■ＤＤ−１Ｖｔｐ　ｌの間の入力電圧Ｖ工で出力電圧Ｖ
。ｔＩＴを反転できるので、インバータ回路のスレッシ
ュホールド電圧Ｖｔ　は Ｖｔｎ　＜Ｖｔ　　＜ＶＤＤ−１’Ｖｔｐ　Ｉなる関係
を有する。is greater than Vtn, N-channel IG FE
T (21 is conductive, input voltage V, H is ■. -I V
P channel IG FE if tp less than 1
T(1) becomes conductive. Therefore, the inverter circuit has an output voltage V at an input voltage V between Vtn and ■DD-1Vtpl.
. Since tIT can be inverted, the threshold voltage Vt of the inverter circuit has the relationship Vtn < Vt <VDD-1'Vtp I.

斯上したインバータ回路は入力電圧■□ヨがスレッシュ
ホールド電圧Ｖｔ　以上か否かの判別回路として利用さ
れる。The above inverter circuit is used as a circuit for determining whether the input voltage □□Y is higher than the threshold voltage Vt.

しかしながら斯るインバータ回路のスレッシ−ホールド
電圧Ｖｔ　を前述した電源電圧■ＤＤ以上に設定したい
要望もある。貼る場合には従来ではしベルシフト回路を
用いてインバータ回路のスレッシュホールド電圧Ｖｔ　
　までレベルシフトして判別する必要があった。However, there is also a desire to set the threshold voltage Vt of such an inverter circuit to be higher than the power supply voltage DD. When pasting, conventionally, a lever shift circuit is used to adjust the threshold voltage Vt of the inverter circuit.
It was necessary to perform a level shift to make a determination.

（ハ）発明の開示 本発明は斯点に鑑みてなされ、電源電圧■ＤＤ以上のス
レッシュホールド電圧Ｖｔ　　を有するインバータ回路
を実現するものである。(C) Disclosure of the Invention The present invention has been made in view of this point, and is intended to realize an inverter circuit having a threshold voltage Vt higher than the power supply voltage DD.

本発明の第１の目的はスレッシ−ホールド電圧Ｖｔ　　
を大巾にレベルシフトしたコンプリメンタリ−ＩＧ　　
ＦＥＴより構成されるインバータ回路を提供することに
ある。The first object of the present invention is to
Complementary IG with a large level shift
An object of the present invention is to provide an inverter circuit composed of FETs.

本発明の第２の目的はスレッシ−ホールド電圧Ｖｔ　を
電源電圧Ｖｆ、Ｄより高く設定したコンプリメンタリ−
ＩＧ　　ＦＥＴより構成されるインバータ回路を提供す
ることにある。A second object of the present invention is to provide a complementary circuit in which the threshold voltage Vt is set higher than the power supply voltages Vf and D.
An object of the present invention is to provide an inverter circuit composed of IG FETs.

本発明によるインバータ回路は第３図から明らかな如（
、デプレッション型のＰチャンネルＩＧＦＥＴ（ＩＩ）
とエンハンスメントＳ？７）ＮチャンネルＩＧ　　ＦＥ
Ｔ（Ｉカで構成され、ＮチャンネルＩＧＦＥＴ（１２）
のスレッシ−ホールド電圧Ｖｔｎを電源電圧■Ｉ、、、
以上に設定したことに特徴を有する。The inverter circuit according to the present invention is shown in FIG.
, depression type P-channel IGFET (II)
and Enhancement S? 7) N channel IG FE
N-channel IGFET (12)
The threshold voltage Vtn of the power supply voltage ■I, ,
It is characterized by the above settings.

に）実施例 本発明に依るインバータ回路は第４図に示す如（、デプ
レッション型のＰチャンネルＩＧ　　ＦＥＴαυとエン
ハンスメント型のＮチャンネルＩＧＦＥＴ（１つとで構
成サレ、両ＩＧ　　ＦＥＴ（Ｉυ（Ｊ７Ｊ（７）ゲート
電極に入力電圧ｖ４が印加され、両ＩＧ　　ＦＥＴ（１
υＱ２＋のドレイン電極より出力電圧Ｖ。ｆｆＴ　　を
取り出している。またＰチャンネルＩＧ　　ＦＥＴ（１
１）のソース電極には電源電圧ＶＤＤ（＋５Ｖ）に接続
され、ＮチャンネルＩＧ　　ＦＥＴ（１２のソース電極
には電源電圧Ｖ１ｇ　（通常は接地）に接続されている
。更にＰチャンネルＩＧ　　ｐｉＴａυのスレッシュホ
ールド電圧Ｖｔｐはデプレッション型であるので正の値
となり、ＮチャンネルＩＧ　　ＦＥＴ（１２１のスレッ
シュホールド電圧Ｖ　ｔ　ｎは電源電圧ＶＤＤ以上に設
定される。(2) Embodiment The inverter circuit according to the present invention is as shown in FIG. Input voltage v4 is applied to the gate electrode, and both IG FETs (1
Output voltage V from the drain electrode of υQ2+. Taking out ffT. Also, P channel IG FET (1
The source electrode of 1) is connected to the power supply voltage VDD (+5V), and the source electrode of N-channel IG FET (12) is connected to the power supply voltage V1g (usually grounded).In addition, the threshold of P-channel IG piTaυ Since the voltage Vtp is a depression type, it has a positive value, and the threshold voltage V t n of the N-channel IG FET (121) is set to be higher than the power supply voltage VDD.

なおＮチャンネルＩＧ　　ＦＥＴ（１２）はゲート酸化
膜の厚みを大きくするかあるいはチャンネル領域に不純
物をドープしてスレッシュホールド電圧Ｖｔｎを所望の
値に設定する。Note that in the N-channel IG FET (12), the threshold voltage Vtn is set to a desired value by increasing the thickness of the gate oxide film or by doping impurities into the channel region.

次に本発明のインバータ回路の動作原理について第４図
を参照して述べる。Next, the operating principle of the inverter circuit of the present invention will be described with reference to FIG.

先ず入力電圧Ｖ□がＮチャンネルＩＧ　　ＦＥＴａ２の
スレッシュホールド電圧Ｖｔｎより大きい場合には、Ｎ
チャンネルＩＧ　　ＦＥＴ（１２６ま導通し、Ｐチャン
ネルＩＧ　　ＦＥＴ（１１）は遮断している。従って出
力電圧Ｖ。ａｒは電源電圧Ｖｓｇレベル（ＯＶ）’にな
っている。次に入力電圧■、やがＶｏｏ　＋　Ｖｔｐよ
り小さい場合には、ＰチャンネルＩＧ　　ＦＥＴ（ｌυ
が導通し、ＮチャンネルＩＧ　　ＦＥＴ（１２）は遮断
している。従って出力電圧■。ＵＴ　　は電源電圧■Ｄ
Ｄレベルになる。First, if the input voltage V□ is larger than the threshold voltage Vtn of N-channel IG FETa2, N
The channel IG FET (126) is conductive, and the P-channel IG FET (11) is cut off. Therefore, the output voltage V.ar is at the power supply voltage Vsg level (OV)'. Next, the input voltage ■, and then If it is smaller than Voo + Vtp, P-channel IG FET (lυ
is conducting, and the N-channel IG FET (12) is cut off. Therefore, the output voltage■. UT is the power supply voltage ■D
Become D level.

依ってインバータ回路の入出力特性は第４図に示す如（
、入力電圧■、がＶｏｏ　＋　Ｖｔｐ以下ではハイレベ
ルとなり、逆にＶｔｎ以上ではローレベルとナリ、イン
バータ回路のスレッシュホールド電圧Ｖｔは両ＩＧ　　
ＦＥＴ（ｌυα渇の遮断時のインビーダンスの比により
ＶＤＤ十■ｔｐからＶｔｎの間に設定できる。Therefore, the input/output characteristics of the inverter circuit are as shown in Figure 4 (
, the input voltage ■ is at a high level when it is below Voo + Vtp, and on the contrary, it is at a low level when it is above Vtn, and the threshold voltage Vt of the inverter circuit is at both IG
FET (lυα) can be set between tp and Vtn depending on the ratio of impedance at the time of blocking the drain.

具体的には■ＤＤを＋５Ｖ、Ｖｔｐを＋ＩＶ、Ｖｔｎを
＋ＩＯＶと設定すれば、インバータ回路のスレッシ−ホ
ールド電圧Ｖｔ　は＋６Ｖ〜λＩＯＶの間に設定できる
。Specifically, by setting DD to +5V, Vtp to +IV, and Vtn to +IOV, the threshold voltage Vt of the inverter circuit can be set between +6V and λIOV.

（ホ）効果 本発明に依ればコンプリメンタＩＪ−ＩＧＦＥＴで構成
されるインパーン回路においてもスレッシュホールド電
圧Ｖｔ　を容易に電源電圧■ＤＤ以上の正の値に設定で
きる。この結果インバータ回路にレベルシフｌ能を持た
せられるので；従来必要としたレベルシフト回路を不要
九でき集積度の向上に寄与できる。(E) Effect According to the present invention, even in an in-pan circuit composed of a complementer IJ-IGFET, the threshold voltage Vt can be easily set to a positive value equal to or higher than the power supply voltage DD. As a result, the inverter circuit can be provided with a level shift function; the level shift circuit required in the past can be eliminated, contributing to an improvement in the degree of integration.

マフＣＮチャンネルＩＧ　　ＦＥＴ（１２１のスレッシ
ュホールド電圧Ｖｔｎの設定によりかなり広い巾で電源
電圧■ＤＤ以上のスレッシュホールド電圧Ｖｔを選択で
きるので回路の設計上有利となる。By setting the threshold voltage Vtn of the muff CN channel IG FET (121), it is possible to select a threshold voltage Vt higher than the power supply voltage DD over a fairly wide range, which is advantageous in terms of circuit design.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のコンプリメンタリ−ＩＧ　　ＦＥＴによ
るインバータ回路を説明する回路図、第２図は第１図の
インバータ回路の入出力特性図、第３図は本発明による
コンプリメンタリ−ＩＧ　　ＦＥＴで構成されたインバ
ータ回路を説明する回路図、第４図は第３図のインバー
タ回路の入出力特性を説明する回路図である。 （１υＩｔｔＰｆ−ｗンネに工Ｇ　　ＦＥＴ、ＩＪ、２
はＮチャンネルＩＧ　　ＦＥＴである。Figure 1 is a circuit diagram illustrating an inverter circuit using conventional complementary IG FETs, Figure 2 is an input/output characteristic diagram of the inverter circuit shown in Figure 1, and Figure 3 is an inverter circuit constructed with complementary IG FETs according to the present invention. FIG. 4 is a circuit diagram illustrating the input/output characteristics of the inverter circuit shown in FIG. 3. (1υIttPf-wn) G FET, IJ, 2
is an N-channel IG FET.

Claims (1)

【特許請求の範囲】[Claims] １、　コンプリメンタリ−絶縁ゲート型電界効果半導体
装置（以下ＩＧ　　ＦＥＴとよぶ。）で構成されるイン
バータ回路において、Ｐチャンネル１Ｇ　　ＦＥＴをデ
プレッション型としＮチャンネルＩＧ　　ＦＥＴをエン
ハンスメント型とし、該ＮチャンネルＩＧ　　ＦＥＴの
スレッシュホールド電圧を電源電圧以上に設定したこと
を特徴とするインバータ回路。1. In an inverter circuit composed of complementary insulated gate field effect semiconductor devices (hereinafter referred to as IG FETs), the P-channel 1G FET is of the depletion type, the N-channel IG FET is of the enhancement type, and the N-channel IG FET is of the enhancement type. An inverter circuit characterized in that a threshold voltage is set higher than a power supply voltage.
JP58003650A 1983-01-12 1983-01-12 Inverter circuit Pending JPS59128828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58003650A JPS59128828A (en) 1983-01-12 1983-01-12 Inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58003650A JPS59128828A (en) 1983-01-12 1983-01-12 Inverter circuit

Publications (1)

Publication Number Publication Date
JPS59128828A true JPS59128828A (en) 1984-07-25

Family

ID=11563347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58003650A Pending JPS59128828A (en) 1983-01-12 1983-01-12 Inverter circuit

Country Status (1)

Country Link
JP (1) JPS59128828A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201460A (en) * 1983-04-30 1984-11-15 Sharp Corp Manufacturing method of CMOS△FET integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201460A (en) * 1983-04-30 1984-11-15 Sharp Corp Manufacturing method of CMOS△FET integrated circuit
JPH0315350B2 (en) * 1983-04-30 1991-02-28 Sharp Kk

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