JPS59127293A - Detecting circuit of signal variation of memory element - Google Patents

Abstract

PURPOSE:To generate the precharging signal of a transition detector system and the internal address signal of an address buffer system in invariably specific order by setting the threshold values of the 1st, the 2nd, and the 3rd comparators in a specified correlation. CONSTITUTION:The output of the 1st comparator 3 is supplied to one input of an NOR gate 51 directly and to the other input through three inverters 52, 53, and 54 in series. The output of the 2nd comparator 4 is supplied to one input of an NAND gate 57 directly and to the other input through three inverters 58, 59, and 60 in series. Then, the output of the 3rd comparator 6 is supplied to the address buffer system 7 through an inverter 8 to generate an internal address signal AI. Then it is assumed that the precharging signal PC should be supplied to restrict a memory circuit after the internal signal AI is supplied. In this case, the threshold values V1, V2, and V3 of the 1st, the 2nd, and the 3rd comparators 3, 4, and 6 are so set that V2<V3<V1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal change detection circuit for a memory element for detecting a change in an input signal and performing a precharge operation inside the memory element.

[Technical background of the invention]

In general, memory devices can be divided into synchronous and asynchronous types depending on the method of initializing the internal state.In the former synchronous type memory device, precharging and discharging of the circuit are performed by inputting a synchronization signal from the outside. By controlling the synchronization signal appropriately, it is possible to initialize to the minimum necessary level and reduce current consumption.In addition, in the latter asynchronous memory element, there is no need to apply a synchronization signal externally. However, in such a circuit, initialization inside the circuit is performed by pulling up each node using a transistor that is always in a conductive state, so it is easy to apply it systemically and is generally easy to use. This results in the existence of a through current, which is undesirable from the viewpoint of reducing the power consumption of the circuit.

For this reason, memory devices are increasingly being used that perform e-initialization by detecting changes in address input signals and generating synchronization signals within the memory element, without applying external synchronization signals. FIG. 1 is a block diagram showing the AT/N input section of such a memory device, and the address signal A
is commonly applied to the transition detector system 1 and the address buffer system 2. The transition detector system I outputs a pulsed precharge signal PC to initialize the internal circuit. In addition, in the address buffer system, an internal address signal AI is generated to select a memory cell in the internal circuit and is provided to the address decoder. In order to operate normally, the transition detector precharge signal and the address signal (
The internal address signal of the sofa system must satisfy certain constraints in terms of timing.Of course, the contents of this constraint vary depending on the circuit system, but for example, after establishing the internal address signal, the precharge signal 0, and conversely, there is a structure in which the internal address signal is given after initializing the internal circuitry in response to the precharge signal.

Generally, memory devices are designed to satisfy the above-mentioned constraints. However, in special situations, such as when an address signal changes slowly over an extremely long transition time, the specified constraints may not be met and an abnormality may occur in the internal operation.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a signal change detection circuit for a memory element that can always generate a precharge signal for a transition detector system and an internal address signal for an address buffer system in a fixed order. The purpose is to

[Summary of the invention]

That is, in the present invention, an address signal applied from the outside is passed through a first comparator that detects a change from a logical value "L" to "H" and a second comparator that detects a change from "H" to u LIf. to the address position detector system, and also to the address position detector system through the third comparator.
, the third comparator, and the threshold value are each designed to satisfy a certain correlation.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. That is, address i=%A
First. The signal is applied to the transition detector system 5 via a second comparator 3.4 in parallel. Here, the first comparator 3 changes the logic value of the address signal A from ``L'' to ``H''.
'', and the second comparator 4 detects a change in the logical value of the address signal from "H" to "L".

And the first. A transition detector system 5 fed with the output of the second comparator 3.4 outputs a precharge signal PC for initializing the internal circuit. Further, the address signal A is sent to the third comparator 6.
via the address buffer system 7 to generate an internal address signal AI. Here's the first one. The circuit threshold value of each of the second and third comparators 3, 4.6 is vI + vt
v v3, and the precharge signal PC is given after the internal address signal AI is given as a constraint on the memory circuit. In this case, each of the above comparators 3, 4.6
The circuit threshold values V, , V2, and V3 are set to satisfy the correlation of the following equation (1).

Vt < Va < Vl (1)
Furthermore, as a memory circuit constraint, when applying the internal address signal AI after applying the precharge signal pc, the following (
2) It may be set so as to satisfy the formula.

■+ < vs < vt """ (2) Figure 3 is a block diagram showing a specific example of the present invention. The transition detector system 5 is constructed by combining an inverter and a gate as shown surrounded by a broken line in the figure. That is, the pressure of the first comparator 3 is directly sent to one input of the NOR gate 5J, and the other input is sent to the three inverters 52.
53.54 are given in series. The output of this NOR gate 51 is then applied to one input of a NAND gate 56 via an inverter 55.

In addition, the output of the second comparator 4 is connected to the NAND gate 57.
It is applied directly to one input of the inverter, and to the other input through three inverters 5B and 59.60 in series. The output of the NAND gate 57 is then applied to the other input of the NAND gate 66 to obtain the precharge signal PC at the output of the NAND gate 56. and the third
The output of the comparator 6 is applied to an address buffer system 7 via an inverter 8 to generate an internal address signal AI.

Furthermore, as a constraint on the memory circuit, it is assumed that it is necessary to apply the precharge signal PC after applying the internal address signal AI. In this case, the first
．． Second. Circuit threshold value vIyv of each third comparator 3, 4.6! Set up tv3.

With such a configuration, the address signal A (Fig. 4(a)
) changes as shown in FIG. 4, the circuit threshold voltage V of the third comparator 6 is reached at time T, and the internal address signal AI (FIG. 4(b)) changes from "L" to "L". 0 changes to ``H'', and the level of the address signal A further increases, reaching the circuit threshold voltage v1 of the first comparator 3 at time Tt, and its output (FIG. 4(C)) changes from ``H'' to ``
This change causes the inverter 52,
There is a certain time delay at 53.54 (Figure 4 (a)) N
It is applied to the other input of OR gate 51.

Therefore, the output of the NOR gate 51 (Fig. 4(,) is that after one input becomes "L", the other input becomes "L".
It becomes "H" only until it becomes H'. On the other hand, N.A.
The output of the NAND gate 57 (FIG. 4(f)) remains at H'', and the output of the NAND gate 56 (FIG. 4(g)) remains at 'H'' only while the output of the NOR gate 5I becomes H''. H”
and is output as a precharge signal PC.

Further, at time T3, when the level of address signal A becomes lower than the circuit threshold value V3j of the third comparator 6, the internal address signal AI becomes 'L'.Then, at time T4, the level of address signal A becomes lower than the second comparator 4
When the circuit threshold value v2 of is reached, the pressure (Fig. 4 (h
)) changes from “L” to “H”. This change is delayed for a certain period of time by the inverters 58, 59, and 60.
Figure (1)) is applied to the other input of the NAND gate 57.

Therefore, the output of the NAND gate 57 (Fig. 4 (f
)) becomes "L" only after one input becomes "H" until the other input becomes "L". Meanwhile, during this period, the output of the NOR gate 51 becomes "L". remains,
Only while the output of the N A N D gate 57 becomes 'LH', the output of the N A N D gate 56 becomes H'' and is outputted as the Precise phrase PC.

Therefore, from the address signal A, 251'''L''
When changing to I(", internal address signal AI is 'L"
After changing from ``H'' to ``H'', the precharge signal PC is output, and when the address signal A changes from @uH to ``L#'', the internal address (iqAI goes from ``H#'' to ``L'') is output.
After changing to , the precharge signal PC can be output.

That is, internal address signal AI and precharge signal PC
The internal circuit can be operated stably and reliably by applying pressure at constant timing.

Note that the present invention is not limited to the above embodiments,
],, Since the circuit threshold value of the third comparator 6 may be set between the circuit threshold values of the second comparators 3 and 4, for example, each comparator 93. A circuit threshold of 4.6 may be set.

〔Effect of the invention〕

As described above, according to the present invention, the precharge signal of the transition detector system and the internal address signal of the address buffer system can reliably satisfy certain timing constraints, thereby stably and reliably controlling the internal circuit. A signal change detection circuit for a memory element that can be operated can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an address input section of a conventional memory device, FIG. 2 is a block diagram showing an embodiment of the present invention,
FIG. 3 is a block diagram showing a specific example of the present invention, and FIG. 4 is a waveform diagram explaining the operation of the block diagram shown in FIG.

Claims (1)

[Claims] A transition detector system that detects a change in an address signal and generates a precharge signal to initialize an internal circuit, and an address buffer system that generates an internal address signal from the address signal. A first comparator is provided to detect a change in the logic value of the address signal from "L" to 1°H, and a first comparator is provided at the input of the transition detector system to detect a change in the logic value of the address signal "H".
A second comparator that detects a change from # to "L" and a third comparator that is provided at the input of the address buffer system and detects a change in the address signal are connected to each other. Signal change detection circuit 0 for a memory device, characterized in that the circuit threshold of the third comparator is set between the circuit thresholds of the second comparators.