JPS59126650A - Master slice semiconductor device - Google Patents

Abstract

PURPOSE:To enable to use the titled device both as a P-N-P transistor and as an N-P-N transistor according to wirings by a method wherein the first N type region and the first and second P type regions are formed on the main surface of a semiconductor substrate, and the second N type region is formed in the first P type region. CONSTITUTION:The first N type region 25, the first P type region 26, and the second P type region 27 are formed on the main surface of the semiconductor substrate 11, and next the second N type region 28 is formed in the first P type region 26. Then, an N-P-N transistor is composed by wiring the N type region 25 as the collector, the P type region 26 as the base, and the N type region 28 as the emitter, and a P-N-P transistor is composed by wiring the N type region 25 as the base and the P type regions 26 and 27 respectively as the collector and the emitter. When these semiconductor devices 29a... are arranged in an array structure, the rate of the P-N-P and N-P-N transistors can be made arbitrary, therefore the wiring pattern of a master slice IC is facilitated, and the elements can be efficiently utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that can effectively configure a master slice IC in which a large number of transistors are arranged in an array.

Conventionally, master slice ICs are NPN and P
Two types of NP transistors are arranged at appropriate ratios, and fixedly set transistors in this arrangement are selectively wired to form a circuit network.

FIG. 1 shows a general NPN transistor constituting such a master slice IC.
There is an N-type region No. 3 which becomes the collector on the identified main surface J2.
Then, a P-type head region J4, which becomes a base region, is formed. Further, an N-type region 15 which is located in this P-type region 4 and becomes an emitter is formed, and this N-type region 13°1
5 and the P-type region 14 constitute an NPN transistor.

As shown in FIG. 2, the PNP transistor has an N-type region J7 as a paste, a P-type region 18 as an emitter, and a P-type head region J9 as a collector on the specified main surface 16 of the semiconductor substrate 1. It becomes like forming.

Figure 3 shows NPN as shown in Figures 1 and 2 above.
) transistor and PNP) using transistor,
This diagram schematically shows an example of a dart array structure when a master slice IC is configured, and has a three-array structure. That is, a large number of PNP) run masks 20 a + 20 b .
1m, 21b, etc. are arranged in the same way.

The master slice IC uses such PNP and NPN
) Arrangement of elements such as transistors 1. Wiring is performed to a fixed mask to form a wide variety of IC circuit networks, which allows the arranged elements to be used efficiently and is configurable. A necessary condition is that there are many types of circuits.

However, depending on the type of circuit, the ratio of the number of required PNP and NPH transistors varies, and the relationship between their combinations also varies. Also, PNP)
Some circuits do not use a run master at all, and vice versa.

In some cases, the circuit may require a PNP (PNP) transistor in the lower stage. Therefore, as in the quad array structure shown in FIG.
If the NP L-transistors were self-tallyed, it would be difficult to effectively support all circuits, and the number of unused or unusable transistors would increase.The purpose of the master slice IC is to cannot be fully achieved.

This invention was made in view of the above points, and it is possible to effectively cope with any type of circuit, efficiently utilize the constructed transistor elements, and fully achieve the original purpose. It is an object of the present invention to provide a semiconductor device that allows a master slice IC to be configured that can achieve this goal.

That is, in the semiconductor device according to the present invention, a first N-type region is formed on the main surface of a semiconductor substrate, and a first N-type region is formed on the main surface of a semiconductor substrate.
and a second P-type region, and a second N-type region is further formed within the range of the first P-type region, and the first and second N-type regions and the NPN or PN by selectively using the first and second P-type regions
This allows a P transistor to be configured.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows the configuration of a semiconductor device that is commonly used for NPN and PNP transistors.
A NW region 25 is formed.

Then, a first P-type region 26 is formed in another part of this main surface, and a second P-type region 27 and a second N-type region 28 are further formed within the range of this P-type region 26. That's how it happens.

That is, the first and second N-type regions 25.2B and the first and second P-type regions 26 are formed on one main surface.
．． The NPN transistor has a first N-type region 25 as a collector, a first P-type region 26 as a base, and a second N-type region 27 as a collector. Configured by designating mold region 28 as an emitter. Also, corresponding to the cross section of (B) in FIG.
By designating the N-type region 25 of the transistor as the pace, the first P-type region 26 as the collector, and the second P-type region 27 as the emitter, a PNP transistor is constructed.

FIG. 6 shows an example of a gate array structure using the above-mentioned shared NPN and PNP transistors, in which semiconductor devices 29a, 29b, etc. as shown in FIG. 4 are mounted on one semiconductor substrate. are arranged in a three-tiered structure. Here, N 1 + N 2. P J * P
The circles indicated by 2+ are the first and second N-type regions 25 m 2 B, and the first and second P-type regions 26, respectively.
．． Corresponds to 27. In other words, if N19N2 and PI are selected and used, it is used as an NPN transistor.
Similarly, if N+PltP2 is selected, it will be used as a PNP type transistor.

That is, if an array structure as shown in FIG. 6 is formed using a semiconductor device comprising NPN and PNP common transistors, the problems that existed in the array structure shown in FIG. 3 described above can be effectively solved. In other words, even if the ratio of the number of PNP and NPN transistors configured in the circuit network is different, there are some that can reliably handle the situation.
PN) Even a circuit network consisting only of transistors can be easily formed. Since all of the arranged transistors can be configured as PNP or NPN, there is no need to unnecessarily route wiring around holes or turns.

FIG. 7 shows another example of a semiconductor device constituting both NPN and PNP transistors, in which, as in the case of FIG. It has a P-shaped head area of 26°27. A deep N diffusion layer 30 is additionally formed corresponding to the N type region 25 of the gate 1, so that it can be used as a cross-under element between the top and bottom N1 regions. If arranged as shown in Figure 8, it can also be used as a cross-under element, but
In this case, the space between the two wooden cores of the second N-type region 28 is used, and there is no need for a deep N diffusion layer as in the case of FIG. 7.

Being able to use it as a cross-under element in this way makes the most of the characteristics of the NPN/PNP common transistor. In other words, because it is a shared transistor,
Although the number of wiring lines constituting a circuit network becomes dense, this method has the effect of alleviating the concentration of wiring lines and enables smooth circuit design formation.

In the case shown in (4) of FIG. 9, a pair of first P-type regions 26a + 26b are set facing each other, and a second N-type region is set for each of the P-type head regions 26a and 26b. Mold area 28
a, 28b, and a pair of first P-shaped head regions 26.
A shared transistor is constructed by arranging and forming a second P-type region 27 between a and 26b.

That is, with this structure, when used as a PNP transistor, it has the characteristic that it can be used as a Manohichi collector PNP transistor as shown in FIG. Depending on the application, this can be used as two PNP transistor elements, and the same circuit can be formed in a smaller area on the master slice, effectively increasing the number of elements that can be accommodated in the mask. shine.

As described above, according to the present invention, it is possible to obtain a semiconductor device that serves as a transistor for both NPN and PNP that effectively constitutes a master slice IC, and in particular, it is possible to obtain a semiconductor device that serves as a transistor for both NPN and PNP, which effectively constitutes a master slice IC. It has great effects in terms of efficient use, etc.

[Brief explanation of drawings]

Figures 1 and 2 show the configurations of conventional NPN and PNP transistors, respectively.
4) The figure shows a planar structure (B), the figure shows a cross-sectional structure, (4) in Fig. 3 shows a conventional gate array structure using the above transistor, and (B) in the same figure shows a part of it. FIG. 4 is a planar structure diagram of a semiconductor device according to an embodiment of the present invention, and FIGS.
A cross-sectional structure diagram corresponding to the a-a line and b-bi in the figure, (4) in FIG. 6 is a diagram showing an example of a gate array structure using the above semiconductor device, and (B) in the same figure is a part of it. FIG. 7 shows a semiconductor device according to another embodiment of the present invention, (4) is a plan view, (B) is a cross-sectional structural diagram, and FIG. 8 shows still another embodiment. Plane structure diagram, (4) in Figure 9
is a planar structural diagram showing still another embodiment, and (B) of the same figure is
(4) is a diagram illustrating a state in which a PNP transistor is constructed using the device shown in the figure. 1 No. Semiconductor substrate 25 First N-type region 2
6... First P-type region, 27... Second P-type region,
28...Second N-type region. Applicant's representative Patent attorney Takehiko Suzue (A) (A) Figure 1 (B) Figure 2 (B) Figure 3. Figure 5 Figure 6 Figure 7 (A) (B) Figure 8 Figure 9

Claims (1)

[Claims] A first N-type region, and first and second P-type regions are formed on the main surface of the semiconductor substrate, and a second N-type region is formed within the range of the first P-type region. , the first
The second N-type region and the first and second P-type regions are wired so as to selectively lead out terminals, so that a PNP or NPN transistor can be selectively formed. Characteristic semiconductor devices.