JPS59126349A - Data communicating system - Google Patents

Abstract

PURPOSE:To prevent missing in a transmission character by connecting addresses of a memory so as to be read in the order of storage, performing interruption processing according to the readout contents, writing information in a write address by the generation of an interruption condition and stopping readout during the interruption processing. CONSTITUTION:An instruction executing section PU of a central processor CC advances an instruction counter and executes the instruction of storage location of a work memory WM designated by the instruction counter. When the execution of the instruction is finished, the own partial address 500 is designated and read and when an interruption signal is read, an instruction counter is jumped to an address where an interruption processing program of the work memory WM is stored to attain the interruption processing according to the contents of the interruption signal. Further, the readout from the own partial address 500 is not performed during the execution of the interruption processing but the writing is continued. Sufficient storage locations are utilized for the partial address area 500 of a common memory RES corresponding to the instruction executing section PU, allowing to attain sure interruption processing without missing the interruption signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [1] The present invention relates to a data communication system, and particularly to a data communication system for performing data communication between, for example, an information processing device and a remote terminal.

In such a data communication system, various devices at a remote terminal are designated according to communication procedures such as polling and selecting, and transmission message blocks are transmitted. Error control is performed for each transmission block, and the information processing apparatus performs real-time multiplex processing on a large number of remote terminal devices. Therefore, in the central information processing device, the operating system requires a complicated communication control program, which requires a large storage capacity in memory, and the processing time required for this is also enormous. This also applies to the terminal device side.

In particular, since a central information processing device multi-processes a large number of tasks in parallel in real time for a large number of remote devices, interrupt processing occurs with high frequency. Therefore, central processing units require complex and sophisticated control programs that are carefully constructed to ensure that interrupt instructions are not lost while processing a large number of interrupt instructions.

OBJECTIVE OF THE INVENTION The present invention aims to eliminate the drawbacks of the prior art and provide a highly reliable and efficient data communication system that does not cause loss of interrupt commands.The following describes the structure of the present invention. Examples include Jl (described below).

Referring to FIG. 1, a loop-shaped data communication network α is shown. The loop α includes nodes Tl, , , Ti, , .

TN, information processing device S as a center processing system,
It includes a communication control device C1, a call processing device D, and a switching device A. Note that the information processing device S, the communication control device C1, the call processing device D, and the switching device A also function as nodes in this loop α. Further, when only two nodes exist, the loop α becomes a round trip transmission path connecting these two mates.

The code flowing through this loop-like transmission link consists of repeated transmission frames of a constant length, each frame consisting of code words according to algebraic laws. Each node T-1: shares one transmission frame, and the information symbol part of the transmission frame circulates between each station in the loop α. The information symbol portion of the transmission frame consists of at least two parts as shown in FIG. That is, a communication information section 100 containing communication information,
A control unit 104 includes call information of the transmission frame 102 and the like. As shown in the figure, the starting code is 1.
06, a redundancy cyclic check (CRC) code 108 and a termination code 110 are added to form a transmission frame 102. The transmission frame is divided into many time slots, each time slot being for securing a channel between each node and switching equipment A.

The call processing device identifies the control information in the transmission frame 102 and supplies call information and other control information to the switching device A through the signal line 130. Switching device A performs switching processing based on this control information and transmits a new transmission frame 10.
form 2. This is done by interchanging the information symbol portions of the transmission frame 102 based on the control information.

Time division time slots are allocated to each node other than the switching device A and the call processing device S, and the communication information unit 10
0 is processed by the switching NA, and the control information section 104 is processed by the call processing device.

The nodes Tl, . . . , Ti, . . . , TN are shown generally as nodes Ti in FIG. S2 and S3, and receiving registers R1, R2 and R3.

The transmission path from the fourth second station Ti-1 of the loop α is the demodulator DE.
The transmission path to the lower station Ti+1 is the modulator MO
It is accommodated in D. As shown in the figure, this node includes a receiving unit R1 that receives a signal from the i-position station, a decrambler DS that descrambles the received scrambled signal,
, a checking unit for checking whether the received code conforms to algebraic coding rules using a function code, for example, the start code 106, of the transmission frame 102, and correcting errors.PR1 serves as a buffer for temporarily storing code words. Shift register SR1 includes a frame forming unit PS that performs algebraic encoding processing such as CRC to form a transmission frame 102, and a scrambler SC that scrambles code words of this frame. These circuits are made up of a series of shift registers.

This circuit configures a transmission frame and performs encoded transmission, and reliably maintains synchronization and performs self-correction of errors to reduce the focus error rate. If self-correction is not possible, retransmission will be performed.

Sending and receiving signals to and from the terminal device 132 is performed using a shift register SR.
The contents of shift register SR are transferred to reception registers R1 to R3 at timings positioned according to the transmission order of each symbol of the transmission frame, and transmitted to transmission register 8.
This is done by updating the contents of the shift register SR with the contents of S1 to S3.

The line sides of the modulator MOD and the demodulator DE may be connected to a two-wire line through a two-wire/four-wire conversion circuit (not shown). In that case, the balance of the conversion circuit is maintained by automatic control and bidirectional transmission is possible.

If there are only two nodes in the loop α, the time slots of the transmission frame are occupied by these two nodes, ie the transmission frame consists of a set of time slots, which are shared by the two nodes. In that case, exchange device A is not required.

Node T1 has a master clock source CLK, which has a voltage controlled oscillator whose fundamental frequency is automatically adjustable. Furthermore, a sample value data processing system is provided, which detects a signal approximately proportional to the timing shift of the receiving bone pit clock from the baseband signal received by the receiving section R. The sampling clock is a pit clock, and its output is a voltage that controls the phase of the clock in a direction in which the timing deviation becomes O, and is supplied to the oscillation control terminal 200 of the master clock source CLK. The master clock source CLK supplies a pit clock from an output terminal 202 and a multiphase operating clock from an output terminal 204 to each circuit as shown.

When the loop-shaped transmission line α shown in FIG.
). As shown in FIG. 4, the digital data exchange network 134 includes a DDX terminator DDCE300 and a DDK having a logical interface function with the DDX.
It is connected to the node shown in FIG. 3 via adapter DDXA. In that case, the connecting wire 304, 308° 308.31
0, 312 and 314 are St and R1 in FIG. 3, respectively.
, S2. R2, S3, and R3, 206 are connected to clock source CLK.

When the node Tl connected to the DDX network +34 becomes a slave station of an external network, the connection 200 from the timing circuit TI to the clock source CLK is not made, and the clock source CLK is read from the DDX adapter DIIXA. It becomes a clock generator operated by the clock supplied to 206.

Timing 1-, when becoming a clock slave, the clock source CLK has a voltage controlled oscillator and the timing circuit T
The connection 208 from I to delay adjuster DEN is deleted.

Further, when operating as a clock master station without connecting a line from the outside, the clock source CLK is not connected to the leads 200 and 20B and becomes an independent clock source. In that case, in order to automatically adjust the reception timing of the transmission code from the lightest node TN, the timing circuit T
It is necessary to perform signal processing on the received baseband signal performed by I, and automatically adjust the delay amount of the demodulator OEM based on the extracted timing information.

The communication control device C has the same configuration as the node Ti, but is capable of accommodating a plurality of lines in the point-to-Φpoint connection format. This is shown in FIG. 5, and the configuration of its main parts may be the same as the node Ti in FIG. 3. The shift register SR1 and the registers R1 to R3 and Sl-S3 may be similar to those shown in FIG. 3, but their number of bits includes only the number of bits necessary for the accommodated terminal.

The point-to-point terminals SRI to SRN are accommodated in the time division multiplexer MPX of the communication control device C via the space division switching network XN. The time division multiplexer MPX receives pit clocks and operating clocks from the clock source CLK on leads 202 and 204, respectively, multiplexes signals from the terminal devices SRI to SRN, sends them to the transmission registers 81 to S3, and also receives the signals from the reception registers. The signals from R1 to R3 are demultiplexed and sent to each terminal SRI to SRN.

Therefore, in the time slot assigned to each terminal, the shift register SR is transferred to the reception registers R1 to R3 all at once.
and shift register S with the contents of the transmit register.
Update uncorresponding digits at each end of R.

The time division multiplexer MPX multiplexes frame synchronization and error correction functions for each line 104 accommodated therein. Time slots for each terminal are sequentially allocated in response to the pit clocks and operating clocks of time division multiplexers MPX boards 202 and 204.

A frame memory FM is connected to the time division multiplexer MPX, and a control status table for each terminal is recorded in this. This is to control transmission of frame formats for transmission and reception for each terminal. Time division multiplexer MPX terminal 5Ri (represented by 'general SRI ~ 5iSR1)
When time slots are assigned to frame memory F
The control state table corresponding to terminal sR1 recorded in M is retrieved, and processing is performed according to the state and the code received from terminal SR1. This performs updating of the control status table and necessary transfers between the transmitting/receiving registers 5t-93 and R1-R3 and the time division multiplexer MPX. The contents of the control status table are for each circuit DS, PR, SR, PS and S shown in Figure 3.
It has a control status display such as C, and the time division multiplexer MPX
updates and maintains these states. In this case, a timing adjustment circuit may be provided on the receiving side of the multiplexer MPX to adjust the timing deviation of the received signal of the point-to-point line.

As shown in FIG. 6, the information processing device S (FIG. 1)
It has a block TB having the same function as Ti shown in the figure. This has registers 5t-53 and R1-R3 and related parts such as DS, PR, SR, PS, SC, etc., and these parts have the number of bits equal to the number of input/output channels of the information processing device S. . That is, path 400
The number of bits is equal to the number of channels between TH and TH multiplied by the number of bits of one channel, and consists of digits corresponding to each input/output channel. The high-speed/low-speed speed conversion device M and the register SRD are connected to the block TB by multiple wires.

These speed conversion device M and register SRD are each divided into input/output subfields, and a large number of channels are assigned to them. The converting device M may be for speed converting a signal with a high pit-ray I, such as an image signal, or in the case of data communication in which the terminal SR1 is acoustically coupled to the telephone line 140 by a telephone handset. It may also include an acoustically coupled modulator/demodulator (MODEM). These I/O channels logically terminate at switch A. Therefore, in the switching device A, switching control processing is performed between each terminal and the logically terminating channel.

As shown in FIG. 6, the information processing device S is centered around a bus 400, and includes processing devices such as a central processing unit CG, a common memory RES, a multiplexer MX, a common file F, a voice response file RE, and a clock generator for interrupt generation. RT
It has devices such as peripheral devices such as.

This system can integrate various functions by assembling transmission frames, and various types of communication systems can be configured by using the information fields of transmission frames. For example, if a private branch exchange is not performed, the terminal SRi is directly connected to the register SRD of the information processing device S or to the input/output side of the conversion device M, and the shift register SR shown in FIG. 5 is not required.

Terminals 5RI-9RN and nodes Ti are logically connected to the information processing apparatus S, and the central processing unit CC performs multiple processes for questions and messages from the terminals and nodes, and for responding to these.

Effective use of each of these functional blocks and related software is achieved by optimizing the arrangement of these blocks and the function of the interrupt processing program. In this embodiment, blocks and lines other than the central processing unit CC operate according to program instructions executed by the central processing unit CC, but these operations are performed in parallel in each block without the involvement of the central processing unit CC. Only when this operation is completed, each block notifies the central processing unit CC of its completion by means of an interrupt signal.

The central processing unit has a work memory H as shown in FIG. 7, and processes the operation results of each block and line using this memory area. Information transfer between this work memory area and each block of the information processing device S is carried out by the central processing unit C.
This is performed by the input/output section To of c. Further, program instructions are executed by an instruction execution unit PU.

The instruction execution unit PU and the input/output unit IO each have their own entrance/exit to the bus 400. However, the work memory WM is shared. Explain how to share it.

The central processing unit CC has an address decoder An, which decodes the signal on the address bus 400-1 and determines the time and input/output unit I to allocate the work memory WM to the instruction execution unit PU.
This is to detect the time allocated to O. The address signal from the instruction execution unit PU and the input/output unit IO is gated by the output of the decoder A[l, and the address signal AD
D is given to the work memory WM. The work memory WM outputs the data read from the storage location specified by the address signal ADD to the signal line R, and the write data is given to the signal line W from the instruction execution unit PU and the input/output unit 0, and is output by the address signal ADD. Stored in the specified storage location.

Information transfer between each block of the information processing device S is performed via the common memory RES. Each block is a common memory RE
The right to access S is given by supplying them with time division time slots from multiplexer MX. Time slots for the central processing unit Cc are allocated to the instruction execution unit PU and the input/output unit IO, and the work memory WM can be accessed in each time slot.

As shown in FIG. 8, the common memory RES has a main memory section, that is, an internal memory H, address registers R1 and R2, comparison circuits CI and C2, a mask change circuit MAS, and the like. In addition, in the same figure, the double line indicates a multi-line signal, and -
Double lines indicate multi-line signals, "." indicates prohibited input, and squares indicate mask signals.

An address bus A is connected to the main memory section MW, and partial addresses PA and the like are given thereto.

The address area of the common memory RES, that is, the storage area of the main memory section MH, is divided into a plurality of partial address areas 500 as shown in FIG. That is, they are provided corresponding to each device. Each partial address area 500 is a partial address PA at a specific address position.
It has a read address 502R and a write address 502W. The read address 502R is the address pointer of the storage location where the partial address area is read, and the write address 502W is the address pointer of the storage location where the partial address area is written.

As a result, each address within the partial address area 500 is logically linked so that reading is performed cyclically in the order in which it was stored. Therefore, each time partial address PA is applied to the common memory, reading and writing are performed according to this cyclic concatenation order. Central processing unit C
A write address pointer 502 for C is given to the old input/output unit IO, and a read address pointer 502R is assigned to the instruction execution unit PU.

6 For example, as shown in the figure, the read address 5゜2R points to the address n+ml for reading the partial address area 500, and the write address 502W points to the address n++i2 for writing to the partial address area 500.
is pointing to.

By the way, the bus 400 of the information processing device S is occupied by each block in a time-sharing manner. This time-division time slot is allocated by changing the logical combination of each bit using an address line 400-1 of several bits.

Bus 400-2 is an input to common memory RIJ, and is composed of the logical sum of output lines from each block.

Bus 400-3 is a parallel output line from common memory RES to each block. Bus 400-4 is common memory RES
This address line is composed of the logical sum of the output lines from each block. Buses 400-2 to 400-4 are bus 40
Only blocks addressed by 0-1 are gated, and characters are transferred between each block as follows.

In the time slot assigned to each block,
In the first half, the partial address PA of the transfer destination block is designated and written, and in the second half, the partial address of the own block is designated and read.

By specifying the partial address in this manner, it is possible to read from the partial address area 500 in the order in which it was written.

As shown in FIG. 8, there are three time slots in this embodiment.
It is divided into phases φ1, φ2 and φ3. The address AA is gated into the main memory section MM by the l-phase φ1 to designate a storage location. As a result, the read address 502R and the write address 5 of the partial address PA of the storage location are
02- is the segment of register R1) 430R and 4
30-, respectively. In the two-phase φ2, input/output data terminals ■ and O of the main memory section MW are connected to the main memory section MM.
Data is transferred to and from the . Whether input/output to/from main memory section M is performed, or whether neither is performed, is determined by the logical values applied to signal lines AC1 and AC2. Signal line ACI is on; (if it is on, phase φ2
When the write address is supplied from the register segment 430W to the address bus A, and the signal line AC2 is activated, the read address is supplied from the register segment 430W at phase φ2.
R is supplied to the address bus A, and depending on the case, data from the data line I is gated in the phase φ2 to the main memory M or from the main memory MW to the data line 0.

On the other hand, 1 is added to the read address and write address of register R1 by adders 432 and 434 in phase φ2 according to the I/1 power and deactivation states of signal lines ACI and AC2, respectively. (corresponding segments of This is done by changing, or masking, the number of bits processed in the circuits 432 and 434. The mask circuit MAS converts the partial address into a mask signal.

In the three-phase φ3, the recording and reading addresses of the register R2 updated in this way are stored in the storage location of the main memory section MH designated by the partial address PA9.

By the way, when the read address 502R (FIG. 9) exceeds the write address 502W, there is no instruction to be read. Comparison circuit C1 compares read address segment 430R and write address segment of register R1) 4
I am constantly comparing it with 30W. When it detects that they are equal, it energizes output 440 and outputs signal AC in phase φ2.
3 and prohibits the AND gate 442 from operating. As a result, the operation of storing data in segment 438R of register segment register R2 is prohibited.

By the way, performing addition modulo a predetermined number as described above means that storage locations in the partial address area 500 are always addressed in a circular manner.

Therefore, for example, if instructions are written to all memory locations included in the partial address area 500,
The contents of write address segment 430W of register R1 are equal to the contents of read address 430R minus 1. At this time, writing to that partial address area 500 must be prohibited. This subtraction is performed by the addition circuit 44.
Comparator circuit C2 compares the two, and when a match is detected, output 442 is activated.

In response, AND gate 444 outputs signal AC4. Other circuits respond to signal AC4 to stop signal AC4. As a result, writing to that partial address area 500 is not performed.

By specifying the partial address in this manner, it is possible to read from the partial address area 500 in the order in which it was written.

The input/output unit of the central processing unit CC 0 is also regarded as one block, and when transferring between two blocks, the instruction execution unit PU transfers a control word specifying code transfer between both blocks to the corresponding one in the main memory RES. Write to partial address PA. Each block reads this control word or instruction from the corresponding partial address PA in the time slot assigned to it and executes the corresponding operation.

When each block completes the operation specified by the control word, the partial address 1 corresponding to the instruction execution unit PU of the central processing unit CC is
/space 500 and write an interrupt signal there.

Note that the interrupt signal is also written to its own partial address by the instruction execution unit PU when the instruction execution unit PIJ executes an interrupt request instruction.

The instruction execution unit PU of the central processing unit CC increments an instruction counter (not shown) therein and executes the instruction at the storage location of the work memory WM specified by the instruction counter. When the execution of the instruction is finished, just before incrementing the instruction counter, it specifies and reads its own partial address 500.

When the interrupt signal is read out by this, the instruction counter is jumped to the address where the interrupt processing program is stored in the work memory WM4, and interrupt processing is performed according to the contents of the interrupt signal. Note that while the interrupt process is being executed, reading from its own partial address 500 is not performed, but writing to it continues.

By providing sufficient storage locations in the partial address area 500 of the common memory RES corresponding to the instruction execution unit PU, interrupt processing can be performed reliably without loss of interrupt signals, and the interrupt processing program can be By providing an interrupt processing function, flexible multiprocessing becomes possible.

When a functional character is received from a terminal device, it is stored in the partial address area 500 of the common memory RES corresponding to the input/output unit IO, and at the same time stored in the partial address area 500 of the common memory RES corresponding to the instruction execution unit PU.
Interrupt signals are accumulated in . As a result, transmission control can be performed on a character-by-character basis, and even if the frequency of interrupts increases, these interrupts will not be lost. Therefore, it is particularly advantageous when programming, etc., which involve frequent conversational communication, is performed using a remote terminal. However, the instruction sent to the line must not be completed with an interrupt, but must be completed with an instruction issued later by the instruction execution unit PU to avoid losing characters.

3 Multi-processing in the information processing device S is performed by an interrupt processing program, which manages a task table consisting of many items. A task corresponds to a channel in a time-division multiplex line, but instead of periodically attaching ties and slots and performing multiple processing as in the case of channels, items in the task table can be referenced by one interrupt signal. done by. That is, the interrupt processing program reads the interrupt signal, updates the associated task table item, and searches for a task table item that is not executing an input/output instruction.

This task table records the contents of the instruction counter of the program interrupted by an interrupt, and according to the priority of the items, the instruction counter of the interrupt processing program is changed to the instruction counter of the interrupted program, and control is controlled by that program. to move to. In this way, the interrupt processing program plays the role of effectively utilizing the time during input/output operations for other tasks.

In this embodiment, as shown in FIG. 6, there is provided an interrupt clock generation circuit RT, which generates an interrupt clock at a predetermined period, for example, every 1 to 2 seconds. If there is no interrupt clock generation circuit RT, if control is transferred to another program as described in 1-1, it will not be possible to manage it unless an interrupt signal is detected. Since interrupts in this case are independent of task item priorities, tasks waiting for control may be ignored. To prevent such a situation, the interrupt clock generating circuit RT generates an interrupt signal at a predetermined period.

By the way, in conventional data transmission lines, when a remote terminal has many devices, these devices are specified by polling or selecting. If you have a device that particularly requires interrupts, set the interrupt key to 1.
It was treated as the same as one device. In this embodiment, such device distinction is achieved by connecting to logical channels created by registers R1 to R3 and 81 to S3, and arbitrary division is achieved by appropriately selecting the field division of the transmission frame. You can create these channels in

One of the remote terminals 5RI-SRH connected to the line
One is shown in FIG. 10 as a representative SRi. This terminal is basically configured similarly to the information processing device S, and similar components are indicated by the same reference numerals. A display device and a keyboard K are connected to the bus 400 via adapters A1 to A3. The adapter A2 is for general characters, and the adapter A3 is for interrupts, and corresponds to blocks RE, F, M, etc. of the information processing device S. However, these blocks generally have a smaller number of processing bits, a smaller speed, and a smaller storage capacity than the blocks of the information processing device S.

The line is a two-wire line in this embodiment, and the line termination device DGE has a modem and a two-wire/four-wire converter.

In this embodiment, automatic correction of typographical errors and incorrect synchronization is performed as an error correction function. This is effective because it requires less hardware. Unlike other transmission systems, where code transfer takes place over long transmission spans, this type of automatic correction is useful for this type of line by reducing the frequency of error correction and by reducing the frequency with which error correction routines are used. This prevents the processing load of multiple control from increasing.

Data transferred between the central information processing unit and the data communication line is transferred to the work memory l of the central processing unit CC and the interface SI? D (Figure 6). However, when there is a large amount of information to be transferred, for example, when the results of batch processing are transferred from the information processing apparatus S by missed communication, it is desirable that this be performed in a manner that overlaps with the operation of the central processing unit cc.

This can prevent the work memory WM from being occupied for a long time.

In this case, the batch processing results are temporarily stored in a temporary storage file, eg, F in FIG. 6, and sent to the communication line through the interface SRD. This is also common memory R
This is done via ES. When writing from the file 7F to the partial address area 500 corresponding to the communication line, the writing progresses quickly, so when the writing catches up to the storage location specified by the read address 502R, the writing from the file F is temporarily stopped.

Reading is performed at the data transmission rate of the communication line. When the read address 502R increments in response to reading, writing from file F is restarted. In this way, transmission to the communication line is performed. In order to synchronize with the reading and writing clocks of the file F, it is necessary to read and write each recording unit of the file F, and to hold the data in a temporary buffer. This is different from a buffer that inputs and outputs one record at a uniform speed and reads the record in the order in which it is written.

Automatic retransmission for error correction is performed by transmitting an automatic retransmission request code on one of a plurality of logical transmission channels formed by segmented information fields of the transmission frame. For example, in the embodiment of FIG.
The channels S2 and S2 are reverse channels for automatic retransmission requests. In this example, the channels of registers R3 and S3 are channels for exchanging control codes such as interrupt signals as well as incoming and outgoing signals.

Establishment of logical links for data communication is generally done by MODEM
, acoustic couplers and telephones with dials. The termination device DCE shown in FIG.
In the case of a DEM and a dial telephone, the line is a loop line. This is illustrated for terminal SRi as shown in FIG. 11.

In the figure, loop α passes through node Ti to loop β
Connected to B. This loop βB is connected to the terminal device IIC.
EB, loop line, terminal device i DCEA, terminal device IIT as terminal SRi via loop βA
Connected to E. This logically forms a bidirectional transmission path. The transmission frame of loop α is divided into slots assigned to node Ti connected to loop α and loop β
There is a field consisting of slots assigned to B.

An operation clock is supplied from the clock source CLK to each block on the loop α side and each block on the loop βB side through leads 204 and 204B, respectively. The ratio of the frequencies of these operating clocks is equal to the ratio of the total number of bits of the transmission frames of loops α and βB. In this case, the time length of the image transmission frame is equivalent to PS'A, SRA,
PRA, O, J: and PSB, SRB, and SPB respectively correspond to the corresponding blocks PS, SR, and PR of the node Ti described above. Registers R1, R2, R3 and S
t, S2°S3 are shared by loops α and βB. Therefore, from the perspective of loop βB, register R1
, R2, R3 serve as transmission registers for shift register SRB, and registers Sl, S2 . S3 serves as a receiving register for shift register SRH. Shift registers SR and SRB have buffer capacities equal to the number of bits of the transmission frames of loops α and βB.

Therefore, the capacity of shift register SRH is
1 to S3, equal to the number of bits of R1-R3, but the shift register SR will be much larger. Therefore, the shift register SR can accommodate the number of lines such as loop βB equal to the number of transmission frame bits of loop α divided by the number of transmission frame bits of loop β.

In that case, the node Tj is the communication control device C in FIG.
Requires common control functions similar to shift register S
In order to prevent the transfer timings of R and SRH from matching, the reset line of the multiphase clock circuit of register SRH is connected to the first phase output of the multiphase clock circuit of shift register SR by signal line eoo. Adjust the operating phase of the multiphase clock circuit.

Similarly, on the terminal SRi side, registers PRB, S
RB: Registers PRA, SRA, corresponding to PSB
PSA, the termination device 11cEA has a modulation/demodulation device, and the blocks CLK, TI, R described with reference to FIG.
, DEN, etc. Also data terminal DTE
are registers R1 to R3, a transmission/reception register SRD similar to Sl-33, and interfaces AI to A3. Display device D, keyboard K, bus 400° multiplexer MX,
It has a central processing unit CC1, a common memory RES, etc., and can communicate with other terminals connected to the loop α.

The line may be a public telephone line or a wireless communication line, and the terminal devices DICEA and DCEB that terminate this line perform modulation/demodulation and line connection control.

Therefore, when requesting a line connection by dialing, it is done at the terminal device DCEA, and when calling a terminal connected to the loop α, it is done at the data terminal [ITE2].

As mentioned above, when a plurality of lines are accommodated in the node Ti, common control like that of the communication control device C is performed, but in that case, the configuration is similar to the information processing device S shown in FIG. become. The common control unit has a common memory RES,
This includes registers PRB and SRB.

Secure a memory area for the operation of each flip-flop in the PSB. These memory areas are secured for each line, updated according to the program executed by the central processing unit CG, and input/output to and from the loops α and βB is performed.

This processing is performed by an interrupt from a real-time clock, and is time-division multiplexed on a plurality of lines. The central processing unit CC of the communication control unit C executes the interrupt wait instruction of the processing program and enters a waiting state until the next real-time clock is input. This clock is supplied by a signal line 600, and its frequency is equal to or an integral multiple of the communication speed of each line.

Lines and related terminal equipment DG in Figure 11
:EA and DGEB are shown in more detail in FIG. The termination devices DCEA and DCEB are respectively connected to a modulator MOD, a demodulator OEM, and a two-wire network such as a balanced network.
It consists of a 4-wire conversion circuit 700. 2-wire/4-wire conversion circuit 7
00 connects a 2-wire line and a 4-wire line to each other and minimizes the return loss in the 4-wire section due to balance balance. It has a control function that automatically adjusts to minimize the relationship coefficient.

On the terminal side, that is, on the DCEA side, the terminal block TB includes registers PRA, SRA, and PSA shown in FIG.
On the information processing equipment side, that is, on the DCEB side, PSB, S
Includes RB, PR8, etc. Terminal device DCEA
is connected to the handset PH of the telephone set, and by performing the normal call operation of picking up the handset P) and dialing, it is connected to the terminal device DCEB on the premises information processing equipment side through the public switched network X.
can be captured. This allows the termination device DC
The modulated wave sent from the modulator MOD of the EH is transmitted to the handset PH.
to confirm the connection.

Switching circuits 702 and 704 connect handset PH and modem M
This is a circuit that performs switching between OD and DEN, and the line is switched between modems NOD and DE by checking the connection described in 1-1.
Connect to the N side. Next, by operating the terminal device DT, it is connected to one channel of the circuit corresponding to the shift register 5RD (FIG. 6). This is done by switching processing in switching equipment A and the call processing equipment through the channels of registers R3 and S3.

FIG. 13 shows the state transition from establishment of such a communication link to restoration to the idle state.

In the same figure, the transition relationship between the control state in the terminal device and each state related to the occurring event is shown, and the states 0 to 6 indicate the state transition relationship when conversational communication is performed by the terminal device, In any state, it is possible to return to state O by putting the handset PH on-hook. Further, states 7 to 11 indicate state transitions of batch transmission in the case of missed communication, etc.

If conversational communication is not performed, the state remains in state 1 and telephone conversation is possible, and in this case, the person on the other end of the conversation is not with the loop α side but with another telephone subscriber.

In state l, the dial may connect to the loop α side, in which case the system is switched to the switching devices 702 and 7 by listening to the modulated wave from the modulator on the called side on the handset PH.
04 switches the modem to the NOD and DE sides. This moves the state from 1 to 2, i.e. P
The user dials the BX and establishes a channel with the information processing device.

When the information processing device receives a response prompting the user to perform an operation, that is, a transmission ready signal, the state shifts to 3. Thereafter, as shown in state 4.5.6, each state is changed by the operation indicated by the transition line between them.

On the other hand, when the terminal is not used, or when requesting batch processing by the information processing device in conversational communication and waiting for a response, the terminal shifts to the absence reset state 7 by operating the absence key and turning it on. When there is an incoming call, the system transitions to state 8 where it prepares an absent response and performs a self-diagnosis. In the self-diagnosis, the terminal 6 automatically diagnoses whether the device is ready for reception, such as turning on the power and setting the paper.

As a result, if reception is possible, the corresponding control code is transmitted and the state shifts to state 9. If reception is not possible, a corresponding control code is sent and the process returns to the absence reset state 87. In the latter case, the central information processing device S (FIG. 1), for example, lowers the priority of the task and moves on to processing other tasks. The central information processing device S monitors the time when there should be some kind of control response from the terminal, and if a receivable signal is not received during this time, the same processing as if a control code indicating that it is not receivable is received is performed.

In state 89, the terminal device receives or waits for reception. If the received message block is good, it sends a control code requesting the next block and moves to the waiting notice ill.
If the block is defective, a control code requesting retransmission of the block is returned and the process moves to the waiting list 810. In this embodiment, since there are two waiting states 10 and 11, it is possible to distinguish between errors in the signal itself requesting blow-off or retransmission. The central information processing device performs monitoring after transmitting a message block and after transmitting an ENQN outer code, which will be described later, and monitors the reception of a control code from the terminal regarding whether to broadcast or retransmit. If there is no response during this time, the make-up code ENQ is sent to register S3.
Then, take measures such as transmitting on the R3 channel. When the terminal device side receives the ENQ code, it retransmits or blows out depending on whether it is in state 10 or 11. If reception of a block is started in states 810 and 11, a transition is made to reception state 9.

From each of these states, the carrier is disconnected to return to the absent reset state 7 and the communication is terminated.

In terminal devices that are not commonly used, the power may be turned off when not in use. For example, in states 0.1 and 7, the power may be off.

In a processing unit that operates only when the power is on, states other than state 3 are handled separately. For example, power off
In the case of F, these states are distinguished depending on whether the absent key is operated or not and whether there is an off-footer or not, and the power is turned on when a call arrives and switching to the modem side is performed. This starts a timer which sets the state identification register to state 2 or 8 when it times out. Depending on the state of the out of office key and phone hook, this can be either an out of office response state of 8 or a PBX
Transition to dialable state 2.

The terminal devices and the central information processing device take the state transition shown in FIG. 13, but the central information processing device manages the state by multiple processing corresponding to communication channels. In other words, state management is performed not only for each communication channel, but also for each task, or work. For example, in a system that allows multiple tasks to be performed on a single communication terminal device, channels and tasks do not correspond one-to-one, and state management must be defined for each communication channel task rather than corresponding to the communication channel. It won't happen. Therefore, two tables, ie, status display, are provided: a channel table in which the state transitions shown in FIG. 13 are defined for each channel, and a channel table in which the state transitions are defined for each task.

Therefore, the state transition in FIG. 13 can be considered as the state transition of one task, and also the state transition of one channel.

9 For example, when one terminal device is used by two people, or when two different tasks are partially performed in parallel, two or more
Additional tasks may occur. For example, after one task performs batch processing, another task may perform conversational communication on the same terminal device. During this time, the batch processing will be completed and the results will be ready to be sent. In Kinomi's embodiment, as soon as a task using a terminal device is completed, the batch processing results are transferred to that terminal.

This is managed by referring to the aforementioned channel table and task table in the central information processing device. Updating and saving of the channel and task tables is performed by the operating system, which functions under the control of the interrupt handler previously described. This operating system includes a communication control program and other service programs. The communication control program performs control and processing so that each item in the channel table satisfies the state 0 transition shown in FIG. Other functions of the operating system refer to and process updates to both the channel table and the task table. More specifically, for example, when batch processing is completed for a certain batch processing task, the channel used by that item in the task table is identified, the channel table is indexed, and that channel is used. Know what other tasks you have. If none of these tasks is currently using that terminal device, the tasks that have completed batch processing will access this terminal. This allows the batch processing results to be sent to that terminal.

Maru-11 According to the present invention, the addresses of the memory of the processing device are linked so that they are read out in the order in which they were stored, and the interrupt processing is performed based on the content read from the read address, and an interrupt condition is generated. writes to the write address, and its reading is stopped during interrupt processing. As a result, even in data transmission where characters are exchanged frequently, such as in programming, data transmission with high utilization efficiency can be realized without losing transmitted characters. Therefore, even in a communication system that accommodates a large number of high-traffic communication lines, highly reliable communication processing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a communication system to which a data communication method according to the present invention is applied, and FIG. 2 is a diagram showing an example of the format structure of a transmission frame used in the communication system of FIG. FIG. 3 is a block diagram showing a detailed configuration example of the node shown in FIG. 1, FIG. 4 is a block diagram showing a configuration example of the interface part between the node and the digital data exchange network, and FIG. FIG. 6 is a block diagram showing a detailed configuration example of the central information processing device in FIG. 1, and FIG. 7 is a block diagram showing the connection with a point-to-point terminal device. 8 is a block diagram showing a specific example of the structure of the common memory in the information processing device. FIG. 9 is a memory structure diagram showing a part of the partial address area in the common memory. Figure 11 is a block diagram showing an example of the configuration of a terminal device; Figure 11 is a block diagram showing an example configuration of a terminal connected to a point-to-Φpoint line; Figure 12 is a block diagram showing a connection between the loop line and the terminal device. FIG. 13 is a state transition diagram showing an example of channel and task state transition control. - Part No. A10. Exchange device C090 communication control device CC, , central processing unit To, , input/output unit M09. Main memory unit 3 PU, , instruction execution unit RES, , common memory S98. Information processing device SRi, , Terminal device Ti, , Node WM, , Work memory 100, , Communication information section 104, , Control information section 500, , Partial address area 502R, , Read address 502W, , Write Address patent applicant Ricoh Co., Ltd. 4 - 1 sun 0 sun 277 - 8 L1') I0

Claims (1)

[Claims] In a data communication method for performing data communication between a plurality of remote terminals and a processing system, the processing system is configured to cyclically link addresses of storage locations so that instructions are read out in the order in which they are written. a storage area provided corresponding to a device including a processing unit and a peripheral device in the processing system, and the storage area stores a read address specifying an address of a storage location from which the instruction is read. a first area; and a second area for storing a write address specifying an address of a storage location to write the instruction; reads an instruction from the location, performs interrupt processing according to the read instruction, and when an interrupt condition occurs in response to a function character received from the remote terminal, specifies the instruction corresponding to the chain side interrupt condition at the write address. A data communication method characterized in that the data is written to a storage location specified by the read address, and reading from the storage location specified by the read address is stopped during interrupt processing.