JPS59124757A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the degree of integration by simple structure by applying voltage of dielectric strength or more to an insulating film, which is formed on a gate electrode for a transistor and with which a word line is brought into contact, connecting the word line and said gate electrode and writing informations. CONSTITUTION:A second polysilicon layer 11 is patterned rectangularly to form a transfer gate 11, and the insulating film 12 is formed around the transfer gate. When a capacitance gate 9 as a first polysilicon layer and a bit line 13 are kept at constant potential and voltage of dielectric strength or more of the insulating film is applied to the insulating film 12, the insulating film 12 is brought to a conductive state at breakdown voltage, and informations can be written selectively to a cell. That is, a dynamic RAM can be utilized as an ROM, and the degree of integration can be increased remarkably more than conventional PROMs.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and in particular to a Guinamisoku type RAM.
The present invention relates to a ROM in which an insulating film that allows selective writing by electrostatic breakdown is formed on a double-layer gate type transfer gate having a structure.

(2) Background of the technology A variety of structures have been proposed for FROM (programmable read-only memory), which utilize irreversible changes in resistance of the storage medium, such as fuse-blown FROM. Things and F A M OS (
Floating gate avalanche
injectionMO3) and MNOS (Met
al n1tride oxide Sem1Con
There are known methods such as M. ducter) that utilize the change in the darkness value of MO3I-Landisk.

Additionally, RAMs with a transfer gate formed on a capacitance gate are also known as RAM (Random Access Memory) structures, but these RO
M and RAM are desired to be highly integrated as density increases.

The present invention forms an insulating film such as an oxide film that can be selectively written by electrostatic breakdown on the transfer gate of the above-mentioned RAM structure to obtain a memory circuit that also functions as a RAM ROM. A memory circuit in which selective writing is performed by causing electrostatic breakdown in an insulating film is proposed by the present applicant, and will be explained below.

(3) Problems with the Prior Art The operating principle of the above memory circuit will be explained with reference to FIGS. 1 to 3.

Figure 1 shows a diagram of performing selective writing by causing electrostatic damage.
Fig. 2 shows the breakdown voltage curve, and Fig. 3 shows the equivalent circuit of the memory cell. In Fig. 1, silicon dioxide (SiO2
), etc., and on the insulating film 2, aluminum (
When an electrode such as A7 is provided and a voltage is applied between the electrode and the substrate from the voltage source 4, the relationship between the current I and the voltage ■ is as shown in Fig. 2. When the breakdown voltage V is reached, the current decreases. It increases rapidly, causing a phenomenon similar to a discharge phenomenon in the insulating film 2, and the electrode 3 and the substrate 1 become electrically conductive.

A cell that actively utilizes this breakdown phenomenon causes electrostatic damage to perform selective writing. 1 is doped or non-doped polysilicon, and in the case of non-doped polysilicon, it may be doped by ion implantation. If such doped polysilicon is used, the breakdown voltage will be 20 to 15 V.
You can select a lower voltage.

As shown in FIG. 3, the memory cell has a capacitance 6 formed with an insulating film on the drain or source side of the MO 35, but with this structure, the degree of integration cannot be increased unless the position where the capacitance 6 is formed is selected appropriately. There was no problem.

(4) Purpose of the Invention In view of the above-mentioned drawbacks, it is an object of the present invention to provide a semiconductor device having a dynamic ROM function by forming an insulating film on a transfer gate of a dynamic RAM structure.

(5) Structure of the Invention According to the present invention, the above object includes a transistor and a capacitor connected to the transistor.

The memory cell includes a word line in contact with an insulating film formed on the gate electrode of the transistor.

To provide a semiconductor device characterized in that information is written by applying a voltage higher than a breakdown voltage to the insulating film to break down the insulating film and connecting the word line and the gate electrode. This is achieved by

(6) Examples of the invention The following two embodiments of the present invention are shown in FIG. 4 and FIG. 5(a).

(bl, (cl, (dl, (e)) will be explained.

FIG. 4 is a side sectional view of the semiconductor device of the present invention, and FIG.
~(el is a plan view, FIGS. 4 and 5 fal~f
This will be explained with reference to e). The substrate 1 is made of silicon or the like, and as shown in FIG. 5A, a filled oxide film 7 (shaded area) is selectively provided on the substrate to form an active region 8.

Next, as shown in FIG. 5, the middle wide part 8a of the active region.

A first polysilicon N9 (shaded area) is formed by patterning to cover 8a' to form a capacitance gate.

Furthermore, as shown in FIG. 5 (C1), a transfer gate (shaded area ).Here, an insulating film, such as an oxide film, is formed on the transfer gate to a thickness of approximately 1000 nm, and insulating films 12a and 12b are formed around the transfer gate.

Next, as shown in FIG. 5(d), arsenic (As) is implanted into the source portion 13 by ion implantation, and is then activated (shaded area), so that the active region 8b becomes a bit line.

Subsequently, an insulating film (not shown) such as PSG is formed on the entire surface with a thickness of 1 μm, and as shown in FIG.
On the surface of 2b.

Holes *a and *b are formed by removing the insulating film.

Next, as shown in FIG. 5 te+, the transfer gate 11
Word lines 14a and 14b passing through insulating films 12a and 12b on a and
etc. is formed.

In the above structure, if the capacitance gate 9, which is the first polysilicon layer, and the bit line 13 are kept at a constant potential, and a voltage higher than the withstand voltage of the insulating films is applied to the insulating films 12a and 12b (usually 15 V or less), as mentioned at the beginning, As described above, the insulating film becomes conductive at the breakdown voltage, allowing selective cell writing.

Reading after writing is done from 1ffl (regular r) RAM
Similarly, charges accumulated on the substrate surface under capacitance gate 9 can be transferred to bit line 13 by applying a voltage to l-transfer gate 11.

That is, it becomes possible to use the RAM as a ROM, and it is possible to dramatically increase the degree of integration compared to the conventional PROM.

Furthermore, by adding this structure to a DRAM cell, it is useful for repairing defective bits by providing redundancy to the cell.

(7) Effects of the Invention As explained in detail in Section 2, the semiconductor device of the present invention allows for high integration with a simple structure, and the presence or absence of item 1q depends on whether or not the insulating film is destroyed. It is possible to create a ROM in a RAM structure in which the values are determined.

In addition, the writing voltage has the characteristic that the insulating film can be broken down at an extremely low voltage of 15 V or less.

[Brief explanation of the drawing]

Figure 1 is a principle diagram of a conventional memory cell in which selective writing is performed by causing electrostatic breakdown, Figure 2 is a voltage-current curve diagram to explain the breakdown voltage in Figure 1, and Figure 3 is a diagram of a voltage-current curve to explain the breakdown voltage in Figure 1. FIG. 4 is a side sectional view of the main part of the semiconductor device of the present invention. FIG. 5 (81-(el is a plan view showing the manufacturing process of the semiconductor device in FIG. 4. 1... Substrate, 2... Insulating film, 3... Electrode, 4... Voltage source, 5...MOS,
6... Capacitance, 7... Filled oxide film, 8... Active region, 9... Capacitance gate, 10... Note ↑, a cell, Ila,
llb...Transfer gate, 12a, 12
b... Insulating film, 13... Source diffusion layer, 14
a, 14 b...Word line. Patent Applicant: Fujitsu Limited Item 4, Figure 5 Procedure γlIi Masai (Method) 1. Indication of the case 1982 Patent side No. 2337! M No. 2, Name of the invention Semiconductor device 3, Relationship with the person making the amendment Patent applicant address Nakahara-ku-1-1-Oda r January, Kanagawa Prefecture Name: Tomiju 1ffI Co., Ltd. 4, Agent ψI (Bug number-211 Address: 1015 Ni-Odanaka, Nakahara-ku, Yozaki-shi, Kanagawa Prefecture March 9, 1982 (Shipping port: March 290, 1983)
) 6. Target of correction 7.7 IIi Correct contents ■) Page 5, line 5 of the specification... Insert r (f) j after r (e) J. 2) Lines 7 and 8 of page 5 of the specification, line 11 of page 6, line 8 of page 8...replace r (e) J with r (f) J. correct. 3) Ming 8 Il'l, page 6, line 9...r(d'
)j should be corrected to "(e)". 4) Correct as shown in the attached drawing, Figure 5.

Claims (1)

[Claims] A memory cell has a 1-run raster and a 1-capacitor connected to the transistor, and a word line is in contact with an insulating film formed on the gate electrode of the transistor, and the insulating film has a withstand voltage of 1-1 or more. 1. A semiconductor device characterized in that information is written by applying a voltage of - to break down the insulating film and connecting the word line and the gate electrode.