JPS59123292A - Method of mounting flat back semiconductor integrated circuit part - Google Patents
Method of mounting flat back semiconductor integrated circuit partInfo
- Publication number
- JPS59123292A JPS59123292A JP57229445A JP22944582A JPS59123292A JP S59123292 A JPS59123292 A JP S59123292A JP 57229445 A JP57229445 A JP 57229445A JP 22944582 A JP22944582 A JP 22944582A JP S59123292 A JPS59123292 A JP S59123292A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- circuit board
- integrated circuit
- flat
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 8
- 238000005476 soldering Methods 0.000 claims description 12
- 238000003780 insertion Methods 0.000 claims description 11
- 230000037431 insertion Effects 0.000 claims description 11
- 239000004020 conductor Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 229920003002 synthetic resin Polymers 0.000 description 4
- 239000000057 synthetic resin Substances 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ラジオ受信機やテレビジョン受像機の電子機
器回路に用いられるフラットパック型半導体集積回路部
品の実装方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in a method for mounting flat pack type semiconductor integrated circuit components used in electronic equipment circuits of radio receivers and television receivers.
従来例の構成とその問題点
半導体集積回路部品（以下、ＩＣと呼ぶ）のフラットパ
ック型パッケージは、第１図に示す如く、半導体素子（
１）をエポキシやシリコンなどの合成樹＼＼
脂でモールド（２）シ、二方向あるいは四方向に外部リ
ード（３）を引出し、これら外部リード（３）の端部を
電子機器における回路基板（４）の所要導電体層（５）
に面接触させ、半田付（６）できるようにしたものであ
る。さらに第２図に、半田付作業を行なう際の外部リー
ド（３）の端部と回路基板（４）の所要導電体層（５）
との対応状態を示している。すなわちフラットパック型
ＩＣの外部リード（３）と回路基板（４）の所要導電体
層（５）とは、Ｘ方向ならびにＹ方向にそれぞれ位置ず
れを生じぜしめることのないように、外部リード（３）
の端部（ａ−ｂ−ｃ−ｄ）と回路基板（４）の所要導電
体層（５）の対応部（ａ’ −ｂ’ −ｃ’ −ｄ’）
とを対向し重ね合わせるようにして、かつ外部リード間
（支）と所要導電体層間（Ｗ′）とが半田付後に位置ず
れによって実質的に狭くなって電気的絶縁が損なわれる
ことのないよう注意する必要がある。Conventional configuration and its problems A flat pack package for semiconductor integrated circuit components (hereinafter referred to as IC) is a flat pack package for semiconductor integrated circuit components (hereinafter referred to as IC), as shown in Fig. 1.
1) is molded (2) with synthetic resin such as epoxy or silicone, external leads (3) are pulled out in two or four directions, and the ends of these external leads (3) are attached to the circuit board ( 4) Required conductor layer (5)
It is designed so that it can be brought into surface contact and soldered (6). Furthermore, Fig. 2 shows the end of the external lead (3) and the required conductor layer (5) of the circuit board (4) during soldering work.
It shows the state of correspondence with. In other words, the external leads (3) of the flat pack IC and the required conductive layer (5) of the circuit board (4) are arranged in such a way that the external leads (3) and the required conductor layer (5) of the circuit board (4) are not misaligned in the X direction and the Y direction. 3)
(a-b-c-d) and the corresponding portion (a'-b'-c'-d') of the required conductor layer (5) of the circuit board (4)
so that they face each other and overlap each other, and so that the distance between the external leads (support) and the distance between the required conductor layers (W') will not become substantially narrower due to misalignment after soldering, and the electrical insulation will not be impaired. You need to be careful.
従来、上記位置ずれを防ぐための通常手段として、第１
図において示す如く、合成樹脂によるモールド（２）部
と回路基板（４）との間に合成樹脂接着剤（７）を塗布
して半田付前に位置ずれかないことを目視で確認し接着
剤（７）を硬化させ、外部リード（３）と回路基板（４
）の所要導電体層（５）とを十分に対向密着したのち、
半田付けを行なうことが成されてきた。Conventionally, as a normal means for preventing the above-mentioned positional deviation, the first
As shown in the figure, a synthetic resin adhesive (7) is applied between the synthetic resin mold (2) and the circuit board (4), and the adhesive (7) is visually confirmed to ensure that there is no displacement before soldering. 7), and then connect the external leads (3) and circuit board (4).
) and the required conductor layer (5) are sufficiently opposed and closely adhered,
It has been accomplished to perform soldering.
しかしこの方法は、最近のＩＣの集積度が増し、ＩＣが
大型化し、外部リード（３）の数が増加するとともに外
部リード間の絶縁距離が短かくなるフラツＬパック型パ
ッケージにおいては、わずがな位置ずれが絶縁不良を起
す囚となることから、目視などによる感応的な作業は精
度の上から合理的なものではない。すなわち外部リード
（３）と回路基板（４）の所要導電体層（５）を精度よ
く対向させて半田付組立を行なうに、人為的感応作業に
依存しない自動組立が可能なパッケージング構成が求め
られている。However, this method is only suitable for flat L-pack type packages, where the integration density of recent ICs has increased, the ICs have become larger, the number of external leads (3) has increased, and the insulation distance between external leads has become shorter. Since misalignment can lead to insulation failure, sensitive work such as visual inspection is not reasonable from the viewpoint of accuracy. In other words, in order to carry out soldering assembly with the external leads (3) and the required conductor layer (5) of the circuit board (4) facing each other with high accuracy, a packaging configuration is required that allows automatic assembly without relying on manual sensing work. It is being
発明の目的
本発明は上述した従来の欠点を除去するもので、簡単な
形状の改良による構成で電子機器の回路基板における所
要導電体層の所定位置にフラットパック型ＩＣを対向密
着させて半田付組立を可能としたフラットパック型半導
体集積回路部品の実装方法を提供するものである。OBJECT OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the conventional technology, and uses a simple configuration that improves the shape of a flat-pack IC by closely contacting and soldering a flat-pack type IC to a predetermined position of a required conductor layer on a circuit board of an electronic device. The present invention provides a method for mounting flat pack type semiconductor integrated circuit components that can be assembled.
発明の構成
上記目的を達成するために本発明では、フラットパック
型半導体集積回路部品の電子機器回路基板への実装にお
いて、フラットパック型半導体集積回路部品の回路基板
に対向する底部に凸起を設け、一方、回路基板の所要位
置に前記凸起に対向する挿入孔を設けて、この挿入孔に
前記凸起を挿入して、回路基板に対するフラットパック
型半導体集積回路部品の位置決めを行ない、以って半田
イ」組立を容易ならしめている。Structure of the Invention In order to achieve the above object, the present invention provides a method for mounting a flat pack semiconductor integrated circuit component onto an electronic equipment circuit board by providing a protrusion on the bottom of the flat pack semiconductor integrated circuit component facing the circuit board. On the other hand, an insertion hole facing the protrusion is provided at a desired position on the circuit board, and the protrusion is inserted into the insertion hole to position the flat pack type semiconductor integrated circuit component with respect to the circuit board. This makes assembly easy.
実施例の説明
以下に本発明の一実施例を第４図、第５図に基づいて説
明する。すなわち第３図は、フラットパック型ＩＣのモ
ールド（２）シた底部（８）に、回路基板（４）に対し
て一方向のみ対称となるその平面が多角形をした凸起（
９）を設けたパッケージ形状の一例である。なお第３図
は詳しく分るように、回路基板（４）に対向する底部（
８）を上面に示している。そして第４図に示すように、
そのパッケージに対して回路基板（４）には、凸起（９
）の多角形と同じ形状をなし且つ周囲がやや大きい、す
なわちフラットパック型ＩＣの前記凸起（９）を挿入し
嵌め合い状態として密着させることができる程度の挿入
孔（ＩＱが構成される。またこの第４図は、上記のフラ
ットパック型ＩＣを回路基板（４）に密着させて半田付
組立を行なった状態を示す。DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 4 and 5. In other words, FIG. 3 shows that the bottom (8) of the mold (2) of a flat-pack IC has a convexity (with a polygonal plane) that is symmetrical in only one direction with respect to the circuit board (4).
9) is an example of a package shape. As can be seen in detail in Figure 3, the bottom part (4) facing the circuit board (4)
8) is shown on the top surface. And as shown in Figure 4,
The circuit board (4) has a protrusion (9) with respect to the package.
) The insertion hole (IQ) has the same shape as the polygon and has a slightly larger circumference, that is, an insertion hole (IQ) that is large enough to insert the protrusion (9) of the flat pack type IC and make it fit tightly. Further, FIG. 4 shows the above-mentioned flat-pack type IC in a state in which it has been assembled by soldering in close contact with the circuit board (4).
第５図は別の実施例を示している。すなわちフラットパ
ック型ＩＣの底部（８）に２つ（複数）のその平面形状
が円形の凸起（１１）が構成されている。この凸起（１
υは回路基板（４）に対して一方向にしか互いに挿入で
きないよう、あらかじめ非対称の位置に構成されている
。すなわち回路基板（４）には２個の挿入孔が構成され
ているが、上記のＩＣを回路基板（４）に密着させて半
田付組立が可能なのは一方向のみである。FIG. 5 shows another embodiment. That is, two (plural) protrusions (11) each having a circular planar shape are formed on the bottom (8) of the flat pack type IC. This convexity (1
υ are configured in advance at asymmetric positions so that they can be inserted into each other only in one direction with respect to the circuit board (4). That is, although two insertion holes are formed in the circuit board (4), the above-mentioned IC can be brought into close contact with the circuit board (4) and assembled by soldering only in one direction.
以上の如く、精度よく位置決めするために、あらかしめ
ＩＣ側の凸起の寸法精度と回路基板の挿入孔の寸法精度
をよく保っておくことが重要である。また半田付する際
、第２図に示したＸ、Ｙ方向の位置ずれは皆無になるが
、半田付が完了するまでに挿入孔からＩＣがはずれたり
しないよう、挿入時、ＩＣの底部に接着剤を塗布して離
脱しないようにし、そして接着剤を硬化させることを行
なうこともできる。As described above, in order to position accurately, it is important to maintain the dimensional accuracy of the protrusion on the IC side and the dimensional accuracy of the insertion hole of the circuit board. Also, when soldering, there will be no positional deviation in the X and Y directions shown in Figure 2, but in order to prevent the IC from coming off from the insertion hole before the soldering is completed, glue the IC to the bottom of the IC when inserting it. It is also possible to apply an agent to prevent separation and allow the adhesive to harden.
発明の効果
以上のように本発明は、フラットパック型ＩＣの底部に
凸起を構成し、且つ対向する回路基板にその凸起を挿入
できる挿入孔を構成する簡単な方法によって、人為的な
目視作業に依存せず、自動的にフラットパック型ＩＣの
組立時の位置ずれを＼
防止し、信頼性の高い電子回路組立を可能とすることが
できる特徴を発輝するものである。Effects of the Invention As described above, the present invention eliminates artificial visual inspection by a simple method of configuring a protrusion on the bottom of a flat pack type IC and configuring an insertion hole through which the protrusion can be inserted into the opposing circuit board. It has the ability to automatically prevent misalignment during assembly of flat-pack ICs without depending on work, and to enable highly reliable electronic circuit assembly.
第１図、＠２図は従来例を示し、第１図はフラン１−パ
ック型ＩＣの回路基板の実装状態を示す斜視図、第２図
は部分拡大図、第３図、第４図は本発明の一実施例を示
し、第３図はフラットパック型ＩＣの斜視図、第４図は
実装状態を示す側面図、第５図は別の実施例を示すフラ
ットパック型ＩＣの斜視図である。
（１）・・・半導体素子、（２）・・・モールド、（３
）・・・外部リード、（４）・・・回路基板、（５）・
・・所要導電体層、（６）・・・半田付、（７）・・・
合成樹脂接着剤、（８）・・・底部、（９） （１１）
・−・突起、萌・・・挿入孔
代理人 森 本 義 弘
第１図
第？図Figures 1 and 2 show a conventional example, Figure 1 is a perspective view showing the mounting state of the circuit board of the Fran 1-pack type IC, Figure 2 is a partially enlarged view, and Figures 3 and 4 are 3 is a perspective view of a flat pack type IC, FIG. 4 is a side view showing a mounted state, and FIG. 5 is a perspective view of a flat pack type IC showing another embodiment of the present invention. be. (1)...Semiconductor element, (2)...Mold, (3
)...External lead, (4)...Circuit board, (5)...
...Required conductor layer, (6)...Soldering, (7)...
Synthetic resin adhesive, (8)...bottom, (9) (11)
・-・Protrusion, moe...Insertion hole agent Yoshihiro Morimoto Figure 1 ? figure
Claims (1)
回路基板への実装において、フラットパック型半導体集
積回路部品の回路基板に対向する底部に凸起を設け、一
方、□回路基板の所要位１４に前記凸起に対向する挿入
孔を設けて、この挿入孔に前記凸起を挿入して、回路基
板に対するフラットパック型半゛導体集積回路部品の位
置決めを行ない、半田付組立を容易ならしめたことを特
徴とするフラットパック型半導体集積回路部品の実装方
法。 パック型半導体集積回路部品の実装方法。[Claims] 1. In mounting a flat pack type semiconductor integrated circuit component on an electronic equipment circuit board, a protrusion is provided on the bottom of the flat pack type semiconductor integrated circuit component facing the circuit board; An insertion hole is provided at a desired position 14 opposite to the protrusion, and the protrusion is inserted into the insertion hole to position the flat pack type semiconductor integrated circuit component with respect to the circuit board and perform soldering assembly. A method for mounting flat-pack semiconductor integrated circuit components, characterized by ease of mounting. A method for mounting pack-type semiconductor integrated circuit components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57229445A JPS59123292A (en) | 1982-12-28 | 1982-12-28 | Method of mounting flat back semiconductor integrated circuit part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57229445A JPS59123292A (en) | 1982-12-28 | 1982-12-28 | Method of mounting flat back semiconductor integrated circuit part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59123292A true JPS59123292A (en) | 1984-07-17 |
Family
ID=16892318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57229445A Pending JPS59123292A (en) | 1982-12-28 | 1982-12-28 | Method of mounting flat back semiconductor integrated circuit part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59123292A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014212196A (en) * | 2013-04-18 | 2014-11-13 | 住友電装株式会社 | Method for manufacturing electronic circuit unit |
-
1982
- 1982-12-28 JP JP57229445A patent/JPS59123292A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014212196A (en) * | 2013-04-18 | 2014-11-13 | 住友電装株式会社 | Method for manufacturing electronic circuit unit |
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