JPS59122216A - Switched capacitor filter - Google Patents

Abstract

PURPOSE:To remove a folded component from a signal and to simplify the necessity of an analog pre-filter by connecting plural switched capacitors in parallel to an input stage. CONSTITUTION:The switched capacitors 11-14 connected in parallel to an input terminal 10 are driven by clock signals phi1-phi4 having different phases by a 1/4 period each. The charge accumulated in the capacitors 11, 12 is transferred to an integrating capacitor 6 by a clock signal phi5. The charge accumulated in the capacitors 13, 14 is transferred to a capacitor 6 by a clock signal -phi5. Because the clock signals phi1-phi4 have the 1/4 period of a clock signal phi0 and the frequency of integer times the frequency of clock signals except the multiples of 4 generates attenuation polars, the clock signals phi1-phi4 are kept at the high level. Namely, the connection of switched capacitor filter to the input stage makes it possible to remove components folded to a passing band.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a switched capacitor filter, specifically a switched capacitor filter that has a prefilter function without increasing the number of operational amplifiers.・Regarding filters. .

[Technical background of the invention and its problems]

Since the switched capacitor filter is a type of sampled data filter, a signal folding component occurs due to sampling, and this appears as a pseudo signal within the passband of the filter. In order to prevent this spurious signal from occurring, it is necessary to remove in advance the input signal having a frequency of 1/2 or more of the sampling frequency.

For this reason, in conventional switched-cabin filters, analog filters such as LC filters and RC active filters are added as prefilters.

In this case, as the passband of the switched cano or sita filter approaches 1/2 of the sampling frequency,
A prefilter with steeper cutoff characteristics is required, but L
The CC filter has a five-dog shape and is poorly compatible with switched carrier two-stage filters, which can be easily integrated into figs and ICs. In addition, the RC active filter that can be made into an IC is
This poses a problem from an economic point of view because the current technology is insufficient in the accuracy that can be achieved with Re elements to obtain steep cutoff characteristics. Therefore, how to construct a switched-9 capacitor filter that can simplify the analog prefilter has become an important issue.

To solve this problem, it is possible to increase the clock signal frequency of the switched capacitor fill, but at the same time, the charge of the sampling capacitor is transferred to the integrating capacitor by the function of an operational amplifier. It becomes necessary to shorten the time required for this purpose. For this purpose, the bandwidth of the operational amplification must be increased in proportion to the increase in the clock signal frequency, which is unfavorable from a circuit design and economic standpoint. In addition, an increase in the clock signal frequency also requires an increase in the capacitance ratio of the capacitor used in the switched capacitor filter. It is economically unfavorable to integrate a capacitor that is larger than the conventional one.

Conventionally, there is a so-called cosine filter, which does not change the clock signal, as a switched cano filter or a shift filter, which has been proposed to solve this problem. (■RoubicGregorian et al.
llllSwitcbed-Capacitor
Decimation and Interpolat
ion C1rcuits 'IEEE Trans,
on C1rcuit11 and Systems
＋Vol.

CAS-27, A6, June 1980 PP,
509-514, ■Japanese Patent Application Publication No. 55-158725, and ■Roubic Gregor1an;
-An Integrated Single-
Chip PCM Voice Codec With
Filters, ”IEFEJour,of
5olid-3tate C1ruits, Vo
l, 5O-16+A4 August 1981 P,
(Refer to 327) All of the telepathically switched canopy filters described in these documents (1) to (2) correspond to those in which a prefilter expressed by the following equation is inserted.

H(Z)=[1+Z-172]/2-(1
) Here, 2 is a variable for two transformations, and by setting z=ej', H(Z) gives the frequency response to a sine wave of angular frequency ω. However, T is the sampling period. Calculating this, I H(e”T) l = C(1-t-cos(ωT
/2))2+r2(GJT'/2))”/2=1 (
ωT/4) I ... (2) 2π force, ω=n〒(n==1t3,5y7...) Therefore, by providing this pre-filter, the analog pre-filter provided in the preceding stage only needs to sufficiently remove input signal components with frequencies that are twice the sampling frequency or more. , its construction is simplified. However, the formula (
More desirable transfer functions other than 1) cannot be realized.

[Object of the Invention] An object of the present invention is to remove aliasing components centered on frequencies of integral multiples, including not only odd multiples but also even multiples of the sampling frequency, and to significantly improve the analog pre-filter for removing aliasing components. The purpose is to provide a switched capacitor i4 filter that can be simplified.

[Summary of the invention]

The switched carrier i4 filter according to the present invention has the following features:
The input signal charge is sequentially sampled once within one cycle period of the first clock signal by a first clock signal having the same period and different phases to a plurality of input stage switched capacitors provided in parallel. The device is characterized in that the sampled signal charge is transferred by the second clock signal to a switched capacitor integrator operated by a second clock signal synchronized with the first clock signal. We add a prefilter expressed by the transfer function , and achieve the same function as our friend. Here αk(k=o, l, 2,
3. ..., N-1) is the capacitance ratio of the capacitor in each of the input stage switched capacitor and switched capacitor integrator, υ. It is determined. Also, N is the second
is the ratio of the first clock signal frequency to the clock signal frequency of .

〔Effect of the invention〕

According to the present invention, among aliasing components accompanying sampling of an input signal, it is possible to remove frequencies at integral multiples of the sampling frequency excluding a specific integer and components in the vicinity thereof. The configuration of the analog prefilter is simplified.

For example, in the switched capacitor filter according to the present invention, the number of input stage switched capacitors is an even number 2n (n is an integer), and the first clock signal for sampling used by each of these capacitors is If we use a shift of T/2n (T is the period of the second clock signal), we can add a pre-filter with an attenuation pole at a frequency that is an integer multiple of f8 divided by 2n-mf8 (m is an integer). You will get the same effect as you did.

In this case, the analog prefilter used in the preceding stage only needs to attenuate aliased components of frequencies of 2 n 16 or more9, and can be very simple. Therefore, it is extremely effective in terms of the structure and economy of the filter.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing the configuration of a switched capacitor filter according to an embodiment of the present invention. In the figure,
10 is an input terminal; 11, 12, 13, and 14 are input stage switched capacitors provided in parallel for sampling the input signal to the input terminal 10; and switches 13 to 13 each made of a MOSFET, etc. ld, 2a~2
d, 3a to 3d, 4a to 4d, and a MOS canopy 1.2.3.4.

These input stage switched capacitors 11°12.1
3. After 14, switches 5a to 5d and capacitor 5
A feedback switched capacitor 15 consisting of a feedback switched capacitor 15 and a switched capacitor integrator 16 composed of an integrating capacitor 6 and an operational amplifier 7 are arranged so that the output of this integrator 16 is guided to an output terminal 17. It has become.

The clock generator 18 is an input stage switched capacitor 1
1.12, 13.14 first clock signals φl, φ2 for sampling.

φ3, φ4 and a second clock signal φ5 for transferring the sampled input signal charge to the switched capacitor integrator circuit and for operating the integrator L1-.
, φ5 are generated.

That is, switches 1a and 1d are activated by clock signal φ1, switches 2a and 2d are activated by clock signal φ2, switches 3a and 3d are activated by clock signal φ3, switches 4a and 4d are activated by clock signal φ4, and switch Ib is activated by clock signal φ4. ,
lc・2 b z 2 c ) 5 a r 5 c is connected to clock signal φ6, switch sb + 3c r
4b + 4c, 5b + 5d are clock signals < 61
1, opening and closing are controlled respectively. Here, as the clock signal waveform is shown in FIG. 2, the first clock signal φ1.

φ2, φ3, and φ4 have a period T, and are sequentially shifted in phase by V4. In addition, the second clock signal φ5
, φ5 is the first clock signal φ.

It has the same period as φ2, φ3, and φ4, and is synchronized with these, but its data is 1/2.

Next, the operation of this embodiment will be explained. The input signal vin applied to the input terminal 10 has a clock signal period T of 1Z.
In four cycles, the signal is first sampled by the clock signal φ4 in the switched capacitor 14, and in the next 1Z4 cycle, it is sampled in the switched capacitor 13 by the clock signal φ3. During these 172 periods, the switched canopies 12 and 11 are generated during the first half 1Z4 period and the second half 1Z4 period of the preceding 1Z2 period A, respectively.
The input signal charges sampled by the clock signals φ2 and φl are transferred to the integrating register 6 by the clock signal φ5, and at the same time the input signal charges are sampled by the clock signals φ2 and φl.
5, the capacitor 5 of the switched feedback capacitor 15 is discharged. Then, during the continuation<1Z2 period C, the input signal charges that had been sampled by the clock signals φ4 and φ3 at the switched canisters 14 and 13 during the preceding 1Z2 period B are sampled by the clock signal φ5. The capacitor 5 of the switched capacitor 15 for feedback is connected in parallel with the integrating capacitor 6 between the output terminal and the non-inverting input terminal of the operational amplifier 7. Ru. At the same time, in this 1Z2 period C, as mentioned above, the input signal charge is sampled by the switched carrier source 12°11 during the first half 1Z4 period and the second half 1Z4 period, respectively, and the switched carrier source for integration is sampled.
The capacitor and f-capacitor 5 of the capacitor 15 are discharged. In this way, the operation in one clock signal period is completed.

In the above operation process, sampling or charge transfer is performed at the timing of the falling edge of the clock signal shown in FIG. 2 (indicated by ↓). Therefore, if the period of the black signal 1 is T, sampling is performed every V4.

The above-mentioned operation of the switched cano filter and the shift filter shown in FIG. 1 can be expressed by the following equation.

C6Vout"'C6Z-1Vout C3Vout
+[CIZ-1-1-C2Z'+c5z-'z+c4
z'+)vin-(4)Here, z-e J07 T
where T is the period of the clock signal, ω is the angular frequency, C1 to C
6 represents the capacitance of capacitors 1 to 6, respectively. When formula (4) is rearranged, the following formula is obtained.

Vout/Vin=Z""[C3+C4Z-'+CIZ
-'+C2Z-'')/[(C6+C5) -C6Z-'
,] -(5) In FIG. 1, the switched capacitors 12°1.3 and 14 are removed, and the switches 1a and 1d are controlled to open and close by the clock signal φ5, and the switches 1b and 10 are controlled by the clock signal φ5. The circuit modified in this way has the same configuration as a normal switched carrier flat filter filter.

FIG. 3 is a circuit diagram showing the structure of a conventional switched capacitor filter obtained by modifying FIG. 1 as described above. In this figure, each symbol represents the same thing as in FIG. 1.

The transfer function of the switched capacitor filter of FIG. 3 can be expressed by the following equation.

Vout/Vin=Z-”C4Z'/[(C6+Cs
) Cl5Z-')-(6) However, C1 is the capacitance of capacitor 1 in FIG.

Equation (6) indicates a low-pass type characteristic. In formula (5), C1=C2=Cs-C4=Ca/4, and in formula (6) TeC'1
=CH> (and the following equations are obtained.

/[(C5+C6) -C6Z') -
(5)'vout/'vin=caZ-7 [(Cs+C
6) C6Z-1)) -(6)' Therefore,
Under these conditions, the switched carrier i+ with the normal configuration
The transfer function of the filter is a transfer function K(Z) expressed by the following formula: K(Z)=(21'2+Zi/2+1+Z '41/4
The product multiplied by -(7) becomes the transfer characteristic of the switched cano four-seater inverter obtained by this embodiment. The attenuation characteristic expressed by equation (7) has an attenuation pole at a frequency that is an integer multiple of the clock signal frequency f, excluding 40 multiples, and the vicinity of the attenuation pole is a stop band. The pass area is around 12 fs. Therefore, such attenuation characteristics can be used as a pre-filter for removing aliasing components of a switched capacitor filter as described above. In other words, if the input stage of a normal switched capacitor filter with a clock signal frequency fs is replaced with a filter having the attenuation characteristic of equation (7), the frequency kfs (k is an integer excluding a multiple of 40) and its vicinity can be It is possible to remove frequency components that fold back into the passband.

As is clear from equation (5), in the configuration shown in FIG. 1, the values of capacitors 5 and 6 do not appear in the numerator of the transfer function. In other words, according to this embodiment, the conventional switched
It becomes possible to add the attenuation characteristic expressed by the numerator of equation (5) without impairing the characteristics of the capacitor filter.

Furthermore, in this embodiment, the first clock signal, that is, the second
Since the pre-sampled charges of the switched carrier and the oscillator are simultaneously transferred to the integrating carrier 6 by the second clock signal every 1/4 cycle of the clock signal, the operational amplifier 7 The gain-bandwidth product may be the same as without implementing the invention.

As mentioned above, the switched capacitor shown in Figure 1
It can be seen that the filter is equivalent to the filter shown in FIG. 3 plus a prefilter expressed by equation (7). That is, in the normal switched capacitor filter shown in Fig. 3, the input stage switched capacitors are replaced with four sets of capacitors whose capacitance is 1/4, and each switch is opened and closed. By simply changing the clock signal for control to the first clock signal mentioned above, the apparent sampling frequency can be quadrupled, and the sampling frequency of the original switched capacitor filter remains unchanged. , (7) is obtained by superimposing the characteristics of the switched capacitor filter shown in FIG. 3. The reason why the capacitance value is set to 1/4 is that the input signal is sampled four times in one period of the clock signal.

FIG. 4 shows the attenuation characteristics of the switched capacitor filter of the present invention obtained as described above. 3 shows the attenuation characteristic of a normal switch-over capacitor filter expressed by equation (6)7, in which the p1 low-pass characteristic is repeated at a period equal to the frequency of the clock signal.

3 shows the attenuation characteristic of the prefilter expressed by equation (7), in which the characteristic having an attenuation pole at kfs is repeated every 4 fs. ■ is the attenuation characteristic of the switched capacitor filter according to the present invention shown in FIG. Therefore, due to the effect of the prefilter mentioned above, the cyclic signal frequency fs (,= 1
/'r)'s 1゜2.3, 5, 6, 7, 9, 10...
(sequence of integers excluding multiples of 4) times and the signals around it are removed, so their aliasing components do not occur within the passband.

As mentioned above, the switched capacitor of this embodiment
According to the filter, the aliasing removal analog filter placed in front of it only needs to provide sufficient attenuation to signals with a frequency that is four times higher than the clock signal frequency. Compared to the case where it is necessary to attenuate signals having a frequency higher than that of the aliasing frequency, the analog prefilter for removing aliased components can be significantly simplified. Furthermore, since the necessary operational amplifiers can be used at the input section of a conventional switched cano-four filter, there is no need to substantially increase the number of operational amplifiers. Furthermore, in this embodiment, the bandwidth of the operational amplifier is reduced because the charge transfer from the modified input is performed at the timing of the conventional switched capacitor filter clock signal, that is, the aforementioned second clock signal. No need to increase.

FIG. 5 is a circuit diagram showing the configuration of a switched capacitor filter according to another embodiment of the present invention. This embodiment uses input stage switched capacitors 21, 22, 23 .
24 are capacitors 1.2.3.4 and two switches Ia, Ib respectively.

This embodiment differs from the embodiment shown in FIG. 1 in that it is constructed by combining 2a, 2b, 3a, 3b, 4a, and 4b. here,
Switch 4=4#a is clocked signal φ11 switch p=
The opening/closing of #-a is controlled by a clock signal φ2, the switch threshold a is controlled by a clock signal φ3, and the switcher 1==fPa is controlled by a clock signal φ4. Also, switch +b and 3p4-=4-b (!:i-4b is clock signal φ5
The opening and closing of each is controlled by the Further, the switches 5gr5br5c and 5d are opened and closed in the same manner as in the embodiment shown in FIG. As shown in Figure 5, the input stage is switched.
When the capacitor is configured, the polarity of the charges transferred to the integrating capacitor 6 is all reversed compared to the case shown in FIG. 1, so the transfer function of the switched carrier or shift filter shown in FIG. is the same as shown in equation (5) with a negative sign added. Therefore, the effect of the embodiment of FIG. 5 is the same as that of the embodiment of FIG. 1, except that the phase of the output signal is opposite to that of the embodiment of FIG.

Therefore, if the phase relationship between the input signal and the output signal is determined in advance, the embodiment of FIG. 1 and the embodiment of FIG.
The degree of freedom in design can be increased by using different embodiments in the figure. Generalize from 2n (n is an integer) to an even number, change the capacitance of each input stage switch and capacitor to 1/2n accordingly, and change the input signal sampling timing to '[/2n( T is the period of the first clock signal (1/fB), which is determined by the first clock signal with a phase shift, and the signal charges of these carriers and capacitors are transferred to the integrating capacitor and capacitor by the second clock signal. Then, (2n)・”-'8 (n e m is an integer)
The effect is equivalent to adding a pre-filter with an attenuation pole at a frequency that is an integer multiple of f. Therefore n
It is clear that by increasing the value of , the analog pre-filter for removing aliased components only needs to attenuate signals with frequencies of 2 nfs or more, and can be made much simpler.

Furthermore, in the above embodiments, the main purpose was to provide a switched capacitor filter that could simplify the analog pre-filter for removing aliasing components, so C,=C2=
By imposing the condition C3=C4, the attenuation pole of the transfer function represented by the numerator of equation (5) is accurately generated at an integral multiple of the clock frequency. However, the configurations of these switched capacitors include the 11 types in the embodiment shown in FIG.
By appropriately mixing the capacitors of type 2 in the embodiment of FIG. 5 and appropriately selecting the capacitance values of these capacitors, the coefficient αk in equation (3) can be set to any real number.

FIG. 6 is a circuit diagram showing an embodiment using this method. In this embodiment, the switched capacitors 11 and 14 in the embodiment shown in FIG.
1 and 34, respectively, capacitor 1 and switches Ia and 1b, and capacitor 4 and switch 4a.

4b, and the other configurations are the same as in FIG. In FIG. 6, the switch 1a is connected to the clock signal φ1.
, the switch 4a is controlled by the clock signal φ4, the switch 1b is controlled by the clock signal φ5, the switch 4b is controlled by the clock signal φ5, and the other switches are controlled by the clock signal φ5.
It is controlled by the same clock signal as the embodiment shown. According to this circuit configuration, switched capacitors 3 and 34 are
The sampled signal charge is transferred to a switched capacitor 32.
33 and is transferred to the integrating capacitor 6 with the opposite sign. Therefore, the transfer function of the switched capacitor filter in FIG. 6 is (5), where the switched capacitor filter 31
and 34, with a negative sign added to the capacitance values C1 and 04. That is, ,/[(C6+C3)-C6Z-1]-(8).

In order to obtain a concrete numerical example, in equation (8), for example, CI =
When C2=C5=C4=C5=C6=1, we obtain.

Equation (8) represents a band-pass type transfer function, and its attenuation characteristic is shown in FIG. In Figure 7, as in Figure 4, ■
Of the seven equations (8), represents the attenuation characteristics other than the prefilter, and ■ is the attenuation characteristic due to the prefilter part, so ■, which is the sum of the attenuation amounts of ■ and ■, is the equation (8)'. Indicates the overall frequency characteristics.

From the above explanation, in the switched capacitor filter according to the configuration of the present invention, each switched capacitor
By appropriately selecting the structure of the capacitor and its capacitance value, (
It is also clear that various transfer functions, generally expressed in the form of equation 3), can be realized as pre-filters and that the position of the attenuation pole can be changed.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of a switched capacitor filter according to an embodiment of the present invention, Fig. 2 is a diagram showing the timing of each clock signal, and Fig. 3 is a conventional circuit diagram that is the basis of the embodiment. 4 is a diagram showing the attenuation characteristics of the switched capacitor filter according to the same embodiment, and FIG. 5 is a diagram showing the attenuation characteristics of the switched capacitor filter according to another embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration of a two-seater filter, FIG. 6 is a diagram showing the configuration of a switched capacitor filter according to still another embodiment of the present invention, and FIG. FIG. 3 is a diagram showing the attenuation characteristics of a filter. 1.2, 3, 4.5, 6... Capacitor 1, 1 a. 1bylcrldp2a+2by2cr2drsa, 3
bp3c, 3d+4ar4br4cr4 d z 5
a p 5 b t 5 cr 5 d '+ Switch, 7-...14.21, 22, 23, 24, 31,
32゜33.34...Input stage switch, capacitor, 15...Switched canopy capacitor for feedback, 16.
...■i----instantaneous-----open----switched capacitor integrator, 17...output terminal. Applicant's agent Patent attorney Takehiko Suzue = A, Quantity -

Claims (4)

[Claims] (1) Multiple input stages switched in parallel
The input signal charge is transferred to the capacitor by the first clock signals having the same period and different phases.
The sampled signal charge is sequentially sampled once within a period, and the sampled signal charge is transferred by a second clock signal to a switched capacitor integrator operated by a second clock signal synchronized with the first clock signal. A switched capacitor filter characterized by having the following configuration. (2) Number of input stage switched capacitors 2n(n
is an integer), and when the period of the second clock signal is T, the phase of the first clock signal is sequentially shifted by T/2n. Capacitor filter. (3) The switched capacitor filter according to claim 1, wherein the capacitances of the input stage switched capacitor and the capacitors in the switched capacitor integrator are all equal. (4) The switched capacitor filter according to claim 1, wherein the input stage switched capacitor and switched capacitor integrator use MOSFETs as switches.