JPS59121868A - Complementary mis static memory cell - Google Patents

Abstract

PURPOSE:To enable to improve the integration by connecting a p type diffused layer of at least one inverter to an n type diffused layer, and forming wirings of high melting point metal or its silicide film extending on the surface of the gate electrode of the other inverter. CONSTITUTION:A p-well 102 is presented on an n type silicon substrate 101, and an n type impurity diffused region 103 and a p type impurity diffused region 104 are connected via a molybdenum silicide 106 through a buried hole. A polycrystalline silicon film 107 is buried under an insulating film 108, and wirings of aluminum alloy metal 109 are formed on a molybdenum silicide layer 106. When thus constructed, the polycrystalline silicon common gate 107 of an MIS type transistor of one inverter and the layer 106 for connecting the layer 104 to the layer 103 are formed in the separate steps. Accordingly, both can be approached to each other. The integration of the aluminum film 109 to be superposed with the layer 106 is performed by the bit lines desired to have low wiring resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an integrated circuit using a CMO8 type semiconductor device.

[Prior art and its problems] In semiconductor devices, especially integrated circuits, there is a desire to reduce the size of elements in order to achieve higher speeds in highly integrated elements, and active research is being carried out in various fields.

High melting metals, gold, or their silicides have lower electrical resistance than polycrystalline silicon or diffusion layers, and unlike aluminum, can withstand high-temperature processes, making it easier to improve the operating speed of equipment and the manufacturing process. It is said to have the advantage of increasing the degree of freedom. However, conventionally, no integrated circuit, particularly a complementary MIS static memory cell structure, has been constructed using a high-melting modified metal or its nolicide.

Figure 1 is a circuit diagram of a conventionally known complementary M'I 8 static memory cell. p, N of p-channel MIS transistor TI and N-channel MIS transistor T2
The gates are commonly connected to form an inverter. p-channel MIS type transistors T3 and N
Similarly, the channel MIS type transistor T4 also constitutes an inverter, and the p-type diffusion layer and the N-type diffusion layer of one inverter are connected to the gate of the other inverter, thereby forming a complementary MIS static memory cell. T5, ']'
Reference numeral 6 denotes a transfer gate consisting of an N-channel MIS transistor, which is connected to bit lines B and 10, respectively. When the p-type widening layer and the n-type diffusion layer are connected with polycrystalline silicon wiring, a PN junction is formed and a diode is generated as shown in Figure 2, making normal operation difficult. A common gate is used in the inverter, and the wiring connects VDD in FIG. 1 to the substrate diffusion layer, the gate's rising pole, and the word line W.
It is conceivable to use a polycrystalline silicon film, vss, bit line B, bottom, and wiring connecting the p-type amended layer and the n-type diffusion layer to the gate of the other inverter to be formed using a hlJ film. However, a large number of HLL wirings are laid out on the cell, which is not suitable for high integration. In other words, due to the limitations of phosphorography due to the reflection from the A and l films and the unevenness of the underlying layer, the
This is because 14 pitches cannot be taken very often.

In contrast, it is conceivable to adopt a multilayer structure of a high melting point metal and an HL film, and to integrally form the wiring between the different conductivity type diffusion layers and the gate electrode using the high melting point metal.

In this case, it is preferable in terms of design to match the work functions of the gate materials of the transistors, so it would be good to do this for both inverters, but the wiring made of high melting point metal in the cell cannot be made too dense as in AIl, so it is still a problem. This hinders high integration.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and it prevents the formation of a PN junction when connecting the different conductivity type diffusion layers of the above-mentioned inverter, and also prevents the formation of a PN junction in the complementary type Ivf I S static memory cell. The purpose is to improve the degree of integration.

[Summary of the Invention] The present invention provides a complementary MIS static memory cell in which the common gates of inverters are arranged opposite each other, in which the p-type permissive layer and the N-diffusion layer of at least one inverter are connected, and the It is characterized by providing wiring (connecting member) extending on the surface of the gate electrode, and using a high melting point metal or its silicide film for the wiring.

[Effects of the Invention] According to the present invention, a wiring is provided that connects the p-type diffusion layer and the n-type diffusion layer of one inverter and extends to the surface of the gate electrode of the other inverter, and this wiring is made of high-melting metal or its like. Since silicide is used, the p-type diffusion layer and the
Forming the wiring in the contact portion of the N-type diffusion layer close to the direct pole of the gate of the inverter is advantageous in terms of achieving higher integration.

゛ Also, it is possible to have a multilayer structure of polycrystalline silicon, connection members, and HL, and the wiring between the diffusion layers and the bit line can be overlapped to significantly improve the degree of integration. If the present invention is applied to one of the inverters and the other is made into hi wiring, contact between the high melting point metal or its silicide and the diffusion layer 7m can be made freely, and between the diffusion layers of the other inverter. distance can be reduced to the limit of isolation.

[Embodiments of the Invention] Embodiment 1 An embodiment of the present invention will be described below with reference to FIGS. 3 and 4 of the drawings.

In Figure 3, the part of the above-mentioned wiring that is silicided with high-melting metal shows the diffusion layer, and the part marked with a circle is the silicide layer of high-melting metal.
FIG. 4 is a cross-sectional view of the section X and -Y in FIG. 63 showing the alloy layer.

P well 102 formed on n-type silicon substrate 101
exists, and the n-type impurity expansion region 103 and the p-type impurity expansion region 104 are connected to the molybdenum silicide 1 through the buried opening.
06. Polycrystalline silicon 107 is buried under the lower insulating film 10B of molybdenum silicide layer 106, and A1 alloy metal 109 wiring is formed on molybdenum silicide layer 106.

In this embodiment, diffusion layers 103 and 104, polycrystalline silicon 107, molybdenum silicide layer 106, and A7 alloy layer 1
09, four layers of wiring are formed, and an extremely highly integrated complementary static MIS memory cell can be realized. That is,
MI13 type transistors Tl, T of one inverter
2 polycrystalline silicon common gate, its p-type forgiveness layer and N
Since the molybdenum silicide layer connecting the mold diffusion layer is made in a separate process, they can be placed close to each other. The same applies to transistors T3 and T4, but
Regarding T3, since the extension of the common gate of the other inverter is provided as a base under the molybdenum silicide layer, the structure is positioned to the right by the pitch between the polycrystalline silicon wirings, but overall it is difficult to achieve high integration. has been achieved.

Further, the bit lines B and B, which are desired to have low wiring resistance, are formed as an Al film overlapping with a molybdenum silicide layer, thereby achieving high integration. Polycrystalline silicon without applying the present invention,
For comparison, a plan view of a two-layer HLL wiring is shown in FIG.

[Other Embodiments of the Invention] In the above-mentioned Embodiment I, an example was shown in which both of the two wirings were made of molybdenum silicide, but it is also possible to use, for example, molybdenum silicide and hl1 alloy. FIG. 6 is a plan view of a static memory cell in which one of the wirings is formed of a molybdenum silicide film and the other is formed of an M alloy film, and FIG. 7 is a sectional view of the X-Y section thereof. As in Example 1, there is a p-well 202 formed on an n-type silicon substrate 201, and an n-type impurity region 203 and an n-type impurity region 204 have molybdenum silicide 206 wiring on one side and A1 alloy 209 wiring on the other side. Connected to many.

Self to C5 indicate contact holes. Here, self, C2
, C5 is drilled in a separate process from C3 and C4, so
The distance between the diffusion layers of the inverter can be reduced.

That is, W, , W3 is the contact hole alignment margin,
W2 indicates the distance between the diffusion layers, but compared to the case where both are used with molybdenum silicide wiring, only Wl and W2 are related. Furthermore, W2 can be reduced at the limit of isolation, resulting in even higher integration. is possible.

Furthermore, by using a metal with a high melting point different from molybdenum silicide or its silicide film in place of the polycrystalline silicon shown in FIG. 3 or FIG. (Drawings omitted)

FIG. 8 shows the molybdenum silicide 106 of the above-mentioned Example 1.
This is an example in which the diffusion layers are connected using a polycrystalline silicon 312 film and a tungsten 311 film selectively formed on the diffusion layers 303 and 304 by vapor phase growth.
It goes without saying that JK is included.

[Brief explanation of drawings]

1 and 2 are complementary MIS static memory cell circuits (Δ, FIG. 3 is a plan view of the complementary MIS static memory cell for detailed explanation of the present invention, and FIG. 4 is the x -ylfr diagram, surface 5 diagram is polycrystalline silicon, A7
FIG. 6 is a plan view of a memory cell provided with wiring, and a cross-sectional view illustrating another embodiment of the present invention. In the figure, 101.201,301 -n-type silicon substrate, ]
02, 202, 302...P well region, 103.
203,303 -n-type impurity diffusion region, 104.2
04.304...p-type 106.206,306...molybdenum nolicide, 1
07.207,307,312...Polycrystalline Irifun, 108,. 105, 205, 208, 110, 210
, 305, 308, 310--Insulating film, 109, 2
09, 309...A7 alloy film, 31 galvanized steel film. Agent: Patent attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Procedural amendment C method) ■, Indication of the case, 1982 Patent Application No. 227419 2, Title of the invention Complementary MIS Static Memory Cell 3 Relationship with the case of the person making the amendment Patent applicant (307”1 Tokyo Shibaura Gunki Co., Ltd. 4 Agent 1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100) 6. 0 figures subject to amendment , ,j-s times 1o61])
7 Contents of amendment 0 Engraving of drawing (no change in content) ・ ・ t”,・ノ °・.

Claims (1)

[Claims] Two inverters each consisting of a p-channel MIS type transistor and an n-channel MIS type transistor having common gates are provided on a semiconductor substrate, and the common gates of the inverters are arranged to face each other, and the n-type diffusion layer of one inverter and the n-type Complementary MI in which the type diffusion layer is connected to the other gate
In the S static memory cell, a wiring is provided that connects the n-type diffusion layers of at least one inverter and the n-type diffusion layer and extends to the surface of the gate electrode of the other inverter, and the wiring is made of a high melting point metal or its like. A complementary MIS static memory cell that uses a silicide film.