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JPS59120884A - Resin-sealed structure of circuit block - Google Patents

Resin-sealed structure of circuit block

Info

Publication number
JPS59120884A
JPS59120884A JP57228953A JP22895382A JPS59120884A JP S59120884 A JPS59120884 A JP S59120884A JP 57228953 A JP57228953 A JP 57228953A JP 22895382 A JP22895382 A JP 22895382A JP S59120884 A JPS59120884 A JP S59120884A
Authority
JP
Japan
Prior art keywords
resin
hole
conductor pattern
chip
active surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57228953A
Other languages
Japanese (ja)
Other versions
JPS6354222B2 (en
Inventor
Kunio Sakuma
佐久間　国雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57228953A priority Critical patent/JPS59120884A/en
Priority to CH694183A priority patent/CH660551GA3/fr
Publication of JPS59120884A publication Critical patent/JPS59120884A/en
Priority to US06/891,084 priority patent/US4644445A/en
Publication of JPS6354222B2 publication Critical patent/JPS6354222B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable the injection of a mold resin over an IC surface by drawing a circuit conductor at the part facing an active surface of an IC chip across a hole for injection of a resin overhanging it. CONSTITUTION:A pattern 8 facing the active surface of an IC chip 1 within circuit conductor patterns 3 and 8 drawn over a base film 4 with bumps 2 is drawn across a molding hole 5 overhung it. This prevents the phenomenon that a molding resin 6 becomes hard to flow as injected from the hole 5 otherwise caused when the pattern 8 is drawn not across the hole 5 thereby enabling the injection of the resin 6 over the surface of an IC.

Description

【発明の詳細な説明】 本発明は腕時計用回路ブロックの樹脂封止構造に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed structure for a circuit block for a wristwatch.

一般的に腕時計用の回路ブロックにおいては、その組み
込まれた集積回路素子以下ＩＣチップと呼ぶ。）をエポ
キシ糸の樹脂により、モールドすることにより、その信
頼性を確保している。Generally, in a circuit block for a wristwatch, the integrated circuit element incorporated therein is hereinafter referred to as an IC chip. ) is molded with epoxy thread resin to ensure its reliability.

従来、腕時計用回路ブロックにおいて、フレキシブル回
路基板にＩＣチップがエースタウンボンディングされて
いる場合、そのＩＣチップのモールド方法は、第２図に
示すように、ベースフィルム４の、ＩＣチップ１の能動
面に対向した部分に穴５を設け、これを利用して樹脂を
流し込み封止する方法が用いられている。Conventionally, when an IC chip is Acetown bonded to a flexible circuit board in a circuit block for a wristwatch, the method for molding the IC chip is as shown in FIG. A method is used in which a hole 5 is provided in a portion opposite to the hole 5, and a resin is poured into the hole 5 to seal it.

しかるにこの方法は、第２図のような場合には問題ない
が、第３図に示すように、■ＣＣチップ１の能動面に対
向した部分に、回路導体パターン７が穴５を取り囲むよ
うに配置されている場合にはモールド用樹脂６の流れが
その導体パターン７に妨げられて、ＩＣ表面全面にモー
ルド用樹脂が流れ込まずに充填不足となる場合が発生す
る、特にこの現象はフェースダウンボンティング後、Ｉ
Ｃチップ表面と導体パターン３の空隙すなわちバンプ２
の高さが小さい場合に顕著である。また、７のようなＩ
Ｃチップの能動面に対向した部分の導体パターン引き回
しは、高密度にＩＣを実装する必要がある場合及び他の
同種の商品とＩＣを共通に用いたい場合などに必然的に
要求される配置である。However, this method has no problem in the case as shown in FIG. 2, but as shown in FIG. If the conductor pattern 7 blocks the flow of the molding resin 6, the molding resin may not flow over the entire surface of the IC, resulting in insufficient filling.This phenomenon is especially common in face-down bonding. After ting, I
C The gap between the chip surface and the conductor pattern 3, that is, the bump 2
This is noticeable when the height is small. Also, I like 7
The conductor pattern routing on the part facing the active surface of the C chip is an arrangement that is inevitably required when it is necessary to mount ICs in high density or when it is desired to use ICs in common with other similar products. be.

本発明はかかる欠点を除去したものであり、その目的は
、前述のようにＩＣチップの能動面に対向した部分にも
回路導体パターンの引き回しがある場合でも、特にコス
トアップすることなく、ＩＣ表面の全域に渡ってモール
ド用樹脂を流し込むことを可能とする方法を提供するこ
とである。The present invention eliminates such drawbacks, and its purpose is to eliminate the above disadvantages, and the purpose of the present invention is to eliminate the need for a circuit conductor pattern on the IC surface without increasing the cost, even if the circuit conductor pattern is routed also in the portion facing the active surface of the IC chip as described above. An object of the present invention is to provide a method that allows molding resin to be poured over the entire area.

以下実施例に革づいて本発明を詳しく説明する。The present invention will be explained in detail below with reference to Examples.

第１図において、１はＩＣチップであり、バンプ２によ
り、ベースフィルム４上に引き回された回路導体パター
ン３及び８にフェースダウンボンディングされている。In FIG. 1, reference numeral 1 denotes an IC chip, which is face-down bonded to circuit conductor patterns 3 and 8 routed on a base film 4 through bumps 2.

８は本発明による構造の回路導体パターンであり、樹脂
注入用の穴５の上をオーバーハング状に横断している点
に特徴がある。Reference numeral 8 denotes a circuit conductor pattern having a structure according to the present invention, which is characterized in that it crosses over the resin injection hole 5 in an overhanging manner.

このような構造とすることにより、穴５よりモールド用
樹脂６を注入した際に、８の導体パターンを包み込む状
態にて樹脂がＩＣ表面に向って流入するため、途中にて
図３の場合のようにさえぎられて流れにくくなるという
現象は解消さえ、ＩＣの能動面全面を樹脂にて完全に覆
うことが可能となる。With this structure, when the molding resin 6 is injected through the hole 5, the resin flows toward the IC surface while wrapping around the conductor pattern 8, so that the molding resin 6 as shown in FIG. This eliminates the phenomenon that the resin is obstructed and makes it difficult to flow, and it becomes possible to completely cover the entire active surface of the IC with resin.

具体列をあげると、穴５の大きさはφ１．３ｍｍ、導体
パターン８の厚みは３５μ、幅は６０μ、ＩＣ１と導体
パターン８との間隙は１５μである。Specifically, the size of the hole 5 is 1.3 mm, the thickness of the conductor pattern 8 is 35μ, the width is 60μ, and the gap between the IC 1 and the conductor pattern 8 is 15μ.

本発明は、同種の商品と共通のＩＣを用いたい場合など
で、設計上ＩＣの能動面に対向した基板の位置に回路導
体パターンを引き回すことが不可欠の場合において、モ
ールドの充填不足の問題を解決することができる点とと
もに、その導体パターンの新構造部についても基板製作
上他のオーバング部と同一工程にて製造することができ
るためコストアップせずに目的を達成できる点などすぐ
れた効果を有するものである。The present invention solves the problem of insufficient filling of the mold when it is necessary to route the circuit conductor pattern at a position on the board facing the active surface of the IC due to the design, such as when using a common IC with similar products. In addition to this, the new structure of the conductor pattern can also be manufactured in the same process as the other overhang parts of the board, so it has excellent effects such as achieving the purpose without increasing costs. It is something that you have.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）（ｂ）は本発明による樹脂による樹脂封止
構造の概念図。 第２図（ａ）（ｂ）は従来の方式による樹脂封上構造の
概念図。 第３図（ａ）（ｂ）は従来の方式による樹脂封止構造の
問題点の説明図。 １・・・ＩＣチップ ２・・・バンプ ３・・・回路基板導体パターン ４・・・回路基鈑ベースフィルム ５・・・モールド用穴 ６・・・モールド用樹脂 ７・・・ＩＣチップの能動面に対向した位置にあるオー
バーハングしていない導体パターン８・・・ＩＣチップ
の能動面に対向した位置にあるオーバーハングした導体
パターン 以上FIGS. 1(a) and 1(b) are conceptual diagrams of a resin sealing structure using resin according to the present invention. FIGS. 2(a) and 2(b) are conceptual diagrams of a conventional resin-sealed structure. FIGS. 3(a) and 3(b) are explanatory diagrams of problems in the resin sealing structure according to the conventional method. 1...IC chip 2...Bump 3...Circuit board conductor pattern 4...Circuit board base film 5...Mold hole 6...Mold resin 7...IC chip active Non-overhanging conductor pattern 8 facing the active surface of the IC chip or more than the overhanging conductor pattern facing the active surface of the IC chip

Claims (1)

【特許請求の範囲】[Claims] フェースダウンボンディングされた集積回路素子を有す
る腕時計用フレキシブル回路素子において、接合された
集積回路素子の能動面に対向する位置のベースフィルム
部に、集積回路素子の外形よりも小さい形状で、かつ回
路の導体パターンがその上をオーバーハング状態で横断
するように引き回された構造の、集積回路素子封止用樹
脂の流入口としての穴を有することを特徴とする腕時計
用回路ブロックの樹脂封止構造。In a flexible circuit device for a wristwatch having an integrated circuit element that is face-down bonded, a base film portion facing the active surface of the bonded integrated circuit element has a shape smaller than the external shape of the integrated circuit element and a circuit-like structure. A resin-sealed structure for a circuit block for a wristwatch, characterized by having a hole as an inlet for a resin for sealing an integrated circuit element, the conductor pattern being routed across the conductor pattern in an overhanging state. .
JP57228953A 1982-12-27 1982-12-27 Resin-sealed structure of circuit block Granted JPS59120884A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57228953A JPS59120884A (en) 1982-12-27 1982-12-27 Resin-sealed structure of circuit block
CH694183A CH660551GA3 (en) 1982-12-27 1983-12-27
US06/891,084 US4644445A (en) 1982-12-27 1986-07-31 Resin mounting structure for an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57228953A JPS59120884A (en) 1982-12-27 1982-12-27 Resin-sealed structure of circuit block

Publications (2)

Publication Number Publication Date
JPS59120884A true JPS59120884A (en) 1984-07-12
JPS6354222B2 JPS6354222B2 (en) 1988-10-27

Family

ID=16884439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57228953A Granted JPS59120884A (en) 1982-12-27 1982-12-27 Resin-sealed structure of circuit block

Country Status (1)

Country Link
JP (1) JPS59120884A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62184494U (en) * 1986-05-15 1987-11-24
JPS6455490U (en) * 1987-10-02 1989-04-05
US5438216A (en) * 1992-08-31 1995-08-01 Motorola, Inc. Light erasable multichip module
US6107689A (en) * 1996-07-30 2000-08-22 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62184494U (en) * 1986-05-15 1987-11-24
JPS6455490U (en) * 1987-10-02 1989-04-05
US5438216A (en) * 1992-08-31 1995-08-01 Motorola, Inc. Light erasable multichip module
US6107689A (en) * 1996-07-30 2000-08-22 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
JPS6354222B2 (en) 1988-10-27

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