JPS59119742A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more specifically, to a method for bringing disconnected wiring in a semiconductor device into a state in which electricity can be supplied. be.

(2) Background of the technology Semiconductor devices, especially semiconductor memories, write information by breaking wiring, that is, by blowing fuses, or by using rows and columns of redundant circuits (spare) to replace defective bits. are doing. On the contrary, it is possible to write information and use spare rows or columns in the same way by making disconnected wires passable. Also,
Dirt array (master slice) integrated circuits are constructed by appropriately forming necessary circuit wiring patterns.

In this case, a new predetermined wiring is formed, but it is possible to form the entire disconnected wiring in advance and make the predetermined wiring energized to obtain the necessary wiring turn. .

(3) Conventional technology and problems A method to enable full conduction of current in disconnected wiring is, for example, to form a structure in which doped polycrystalline silicon is placed on both ends of non-doped polycrystalline silicon, and this is exposed to radar light, etc. There is a method of locally irradiating and heating energy rays to cause re-diffusion of impurities from doped polycrystalline silicon to non-doped polycrystalline silicon, making it possible to conduct electricity (M
inato etal.

l5SCC1981゜5ESSION 1. WAM 1
．． 2 Hitachi).

However, this method has a limitation in that only doped polycrystalline silicon can be used as the conductor material, which causes an rc problem when reducing wiring resistance.

(4) Purpose of the Invention The purpose of the present invention is to propose a method for bringing a disconnected wire into a state in which electricity can be supplied without the above-mentioned problems.

Another object of the present invention is to propose a method for manufacturing a semiconductor device in which the sand distribution process of the semiconductor device is completely adapted to change the wire from a disconnected state to an energized state.

(5) Structure of the Invention These objects are aimed at forming a non-doped polycrystalline silicon layer across layers in the wiring formation process of a semiconductor device;
On this polycrystalline silicon layer, the first. A high melting point metal silicide layer is formed in a region corresponding to the portion spanning the second conductive layer, and a) the optical surface of the high melting point metal silicide layer is heated and oxidized with an energy beam in an oxidizing atmosphere to form an oxide. a first layer and a high melting point metal silicide layer. This is achieved by a method for manufacturing a semiconductor device, which is characterized in that it includes connecting a second conductor layer.

In the present invention, a high melting point silicide layer is formed on a silicon layer, and when this silicide layer is thermally oxidized, a silicon dioxide (StO2) layer is formed on the silicide layer, and at the same time, the thickness of the silicon layer under the silicide layer is reduced. The phenomenon in which this high melting point silicide layer sinks is essentially utilized.

(6) Embodiments of the invention Hereinafter, the present invention will be described in detail by way of embodiments of the invention with reference to the accompanying drawings.

The wiring forming step in the method of manufacturing a semiconductor manufacturing device according to the present invention is performed as follows.

As shown in FIG. 1, an insulating layer (for example, silicon dioxide, silicon nitride) 2 is formed on a semiconductor substrate (silicon wafer or gallium arsenide wafer) 1 by a thermal oxidation method, chemical vapor deposition method (CVD method), etc. do. Next, a non-doped l-crystalline silicon layer 3 with a thickness of about 200 nm is formed on the insulating layer 2 by low pressure CVD. In order to make a part of this polycrystalline silicon layer 3 a conductive layer for wiring by doping with impurities (A8), a photorenost layer 4f having a wiring pattern is formed on the polycrystalline silicon layer 3 (Fig. 1). Impurities (A8) are selectively implanted into the polycrystalline silicon layer 3 by ion implantation using the photorenost layer 4 as a mask. As a result, conductor layers 5A and 5B as shown in FIG. 2 are formed, and non-doped polycrystalline silicon layer 3 is present as an insulator between conductor layers 5A and 5B.

In this state, the polycrystalline silicon layer 3 surrounds the conductive layers 5A and 5B as shown in FIG. 3 in a plan view. Therefore, the conductor layer 5A.

5B is in a disconnected state.

After removing the photoresist layer 4'z, a thin non-doped polycrystalline silicon layer 6 is formed on the polycrystalline silicon layer 3 and the conductor layers 5A and 5B to a thickness of 20 nm to 30 nm by low pressure CVD (FIG. 2).

Since this polycrystalline silicon layer 6 is non-doped, it has an insulating property, but if the thickness is thinner than 20 nm, the withstand voltage becomes a problem. Furthermore, if the thickness is 30 nm or more, it will take time to oxidize in the post-process.

Next, the high melting point metal silicide layer 7 is formed by sputtering or CV
Conductive layer 5A is formed on thin polycrystalline silicon layer 6 by method D.
and 5B in the corresponding region of the polycrystalline silicon 3 and the adjacent conductor layer portion. This state is shown in FIGS. 2 and 3.

The high melting point metal silicide layer 7 is made of MoSi 2 or Oka 1
2 and to form the shape shown in FIGS. 2 and 3, it is preferable to use photoresist or to form by a foot-off method. Note that the thickness of the high melting point metal silicide layer 7 is preferably 200 nm or more, since the resistance value is large if it is thin.

Next, in an oxidizing atmosphere, that is, in a state where oxygen is flowing, an energy beam (for example, argon laser or YaG laser) is applied to the high melting point metal silicide layer 7 and its vicinity.
8 and heat it. As a result, the high melting point silicide layer 7 is oxidized and a silicon dioxide layer 9 is formed on the surface (FIG. 4), and at this time, the silicon in the high melting point metal silicide layer is oxidized and comes out, forming the thin polycrystalline silicon layer below. The thin polycrystalline silicon layer 6 under this silicide layer 7 disappears in order to absorb the silicon of the / layer. In this way, the fourth
As shown in the figure, the high melting point metal silicide layer 7 is connected to the conductor layer 5.
A and 5B are in contact with each other, and the α-conducting layers 5A and 5B are in contact with each other.
are electrically connected. Even the thin polycrystalline silicon layer 6 is oxidized where it is hit by the radar (FIG. 4). By irradiating only the necessary portions of the large number of high-melting point metal silicide layers with energy beams, those portions change from a disconnected state to a state in which current can be applied, and a predetermined circuit configuration is completed.

In the above embodiment example, a semiconductor substrate is used, but sapphire or glass can be used as the substrate, and in this case there is no need to form an insulating layer.Furthermore, it is also possible to use metal as the substrate. Yes, in this case an insulating layer is required. Mo is used instead of doped polycrystalline silicon for the conductor layer.
Alternatively, it may be made of a high melting point metal such as W, and the insulator portion may be made of SiO2 or Si in place of non-doped polycrystalline silicon.
, N4 may be used. When using these materials, it is necessary to form them using an appropriate process different from the above-mentioned forming process.

Example silicon wafer 1 is thermally oxidized to form a silicon wafer 3
(thickness: 200 nm). A conductor layer 5A of polycrystalline silicon doped by ion-implanting A8 ions using the photoresist layer 4 as a mask.

5B (ion implantation energy: 150 keV).

After removing the photoresist layer 4, a thin non-doped polycrystalline silicon layer 6 (20 nm thick) was formed on the entire surface by low pressure CVD. A photoresist layer (not shown) is formed by applying a photoresist to the surface and developing it to form a photoresist layer (not shown), and a high melting point silicide layer of MoS 12 is formed on the entire surface by sputtering two types of MO tardasotho and Stmetat at the same time. and a photoresist layer and Mo5 on it
t layer is removed and a layer λ is formed above between the conductor layers 5A and 5B
10S1 layer 7 is left. The silicon wafer 1 was held at 450° C., and the Mo 812 layer 7 was irradiated with argon radar 8 (5 W, 1 second) in an oxygen atmosphere. Mo5t layer 7
An 8102 layer 9 (40 nm thick) is formed on top, while
Under the MO8i2 layer 7, the thin polycrystalline silicon layer 6 was removed, and the Mo8 layer 7 came into contact with the conductor layers 5A and 5B to connect these conductors 5A and 5B.

(7) Effects of the Invention By the manufacturing method according to the present invention, it is possible to form an alternative to a fuse in a fuse-cut type ROM or a RAM with a redundant circuit. Further, the same function can be achieved without the usual wiring/'Pter/forming process (mask fabrication, A/=digital, photorin process) on the gate array.

[Brief explanation of drawings]

1, 2, and 4 are schematic partial sectional views of a semiconductor device illustrating a wiring formation process in a method for manufacturing a semiconductor device according to the present invention, and FIG. 3 is a plan view of FIG. 2. It is. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Insulating layer, 3...Non-doped polycrystalline silicon layer, 5A, 5B...Conductor layer, 6...
- Non-doped thin polycrystalline silicon layer, 7... High melting point metal silicide layer, 8... Energy line, 9... Oxide layer. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akira Yamaguchi

Claims (1)

[Claims] 1. The wiring formation process of a semiconductor device is as follows (a) ~): (
b) forming an electrically insulated eleventh second conductor layer on the substrate; A non-doped polycrystalline silicon layer is formed over the second conductor layer, and the first conductor layer is formed on the polycrystalline silicon layer. A high melting point metal silicide layer is formed in a region corresponding to the portion spanning the second conductive layer, and a) the surface of this high melting point metal silicide layer is heated and oxidized with an energy beam in an oxidizing atmosphere to form an oxide layer. The high melting point metal silicide layer is completely formed and the high melting point metal silicide layer is formed in the first.
A method of manufacturing a semiconductor device, comprising: connecting a second conductor layer.