JPS59119329A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To reliaze complete AC driving and to obain long-life and high-reliability display free of a decrease in contrast by varying an AC voltage impressed to liquid crystal symmetrically between the positive and negative voltages in a display state by using a transistor matrix array. CONSTITUTION:A voltage of 0V is applied in the display state as the picture signal voltage V(Yj) of a data line Yj, and a voltage VD/2 is also applied as a repetitive voltage with a crest value VD. At this time, a voltage VC of 0V is applied to the counter electrode of liquid crystal 22 and CP is so set that the voltage drop DELTAV=CP.VG/(CS+CF) (where CS and CP are the capacity values of a capacitor 23 and parasitic capacitance 25 and VG is the crest value of a gate pulse impressed to an address line Xi) across the parasitic capacitance 25 is about VD/2. Consequently, the AC driving voltage phii,j applied to the liquid crystal 22 in an on state is symmetrical between the positive and the negative voltage to obtain the long-life and high-reliability display having no decrease in contrast.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an AC-driven liquid crystal display device using a transistor matrix array.

[Technical background of the invention and its problems]

2. Description of the Related Art In recent years, liquid crystal display devices in which switching transistors are arranged in a matrix array and used as a driving circuit have been attracting attention.

In this method, all image information is accumulated in each dot of a switching transistor matrix provided on a substrate.
This method attempts to obtain a desired image by displaying this image information at a position corresponding to each dot of a liquid crystal provided on a matrix array, and is a method using CRJK, which has been the mainstream of conventional display devices. In principle, a much thinner display device can be realized compared to the conventional method.

In addition, the display principle of CRT is that a high-energy electron beam collides with a fluorescent material to emit light, so the entire screen is not always displayed, and the CRT takes full advantage of the afterimage phenomenon of the human eye. There was a problem with visibility due to flicker noise, etc.

On the other hand, a liquid crystal display device using a transistor matrix displays information almost all the time, and can provide a more natural screen than a CRT. Furthermore, compared to CRT, it has features such as a flat screen, no need for a high-voltage power supply, no need for a vacuum area, and because it is an all-solid-state device, it is small, lightweight, and has sufficient strength. .

FIG. 1 is a schematic diagram showing the basic configuration of a transistor matrix array. The display screen is divided into a matrix of m lines vertically and n lines horizontally, with a total of m·n unit pixels. Intersection of each matrix C11+ C12...C
Jjj...Cmn is composed of a pixel circuit with a memory function using switching transistors, in which image information of each pixel is stored, and according to this information, each of the liquid crystals provided on the matrix array is Display is realized in areas corresponding to pixels.

A specific pixel circuit having a simple configuration as shown in FIG. 2 is used. This is because in order to obtain a high-definition display screen, the size of the matrix m''n becomes very large, so a simpler circuit is desired in order to create a matrix array with a high yield. In FIG. 2, 21 is a switching transistor, 22 is a liquid crystal layer, and 23 is a capacitor for accumulating image signals.
Reference numeral 24 denotes a capacitor/P capacitor for cutting a DC component used when AC driving the liquid crystal, and is sufficiently large compared to the weight of the liquid crystal layer.

The dart of the transistor 2 is connected to the first address line Xi, and the source electrode is connected to the jth data line Yj. Address line Xi and data line Yj are connected to power supplies v(XI) and V(Yj), respectively. Transistor 21 on address line Xi? When a signal to turn on is input, the channel of the transistor 21 becomes conductive, and at this time the data line Y
The image signal prepared in j is stored in the capacitor 23, and the signal is stored in the capacitor 23 while the dart voltage v(Xi) is zero. The liquid crystal 22 is driven in accordance with this accumulated image signal. Note that all other transistors on address line i also enter the QN state at the same time, and the image signals V(Yi) and V(Y2)-v(Yn) prepared on each printer line Yj at that time become Each pixel circuit Ci l+ Ci 2...C3n V? - Accumulated. Similarly, X Todo' + Xl +2 t・
In this way, the image signals on each address line are accumulated one after another, and the signals on all sides are written.

FIG. 3 schematically shows how the image signals Vdi and Vdi+1 are written in the pixel C1 and jt CH++ lj. Image signal φ1 in FIG. j.

At φi+1, j, the solid line shows the voltage waveform during ideal operation. That is, pixel C1,
The image signal of j starts writing at time t (1), and at the same time the writing ends at tij+ΔT, the dart voltage v(Xi) becomes zero, and then one field period T
Until the image signal penetrates into C1j again at time ji2 after f, φi,'' will be held as the image signal Vat.

However, in reality, as shown in FIG. 2, there is a parasitic capacitance 25 between the dart and drain of the switching transistor 21, so the moment the dart cruise becomes zero, the effect of this parasitic capacitance 25 causes the capacitance to increase. In the voltage φi,j stored in 23, a voltage drop ΔV as shown by the broken line in FIG. 3 occurs.

By the way, the materials for switching transistors are:
Si, CdSe in crystalline, polycrystalline, and amorphous states
, Te, CdS, etc. are used. Especially in recent years,
In order to increase the area and reduce costs of transistor matrix arrays, thin film transistors (TPTs) using polycrystalline semiconductors and amorphous semiconductors, which can be manufactured using low-temperature processes, are being developed.
) is attracting attention. Since the field effect mobility of these TPTs is considerably lower than that of MOS transistors using crystalline Si gold, in order to fully write the entire image signal to the capacitor within the time ΔT shown in Figure 3, it is necessary to It is necessary to make the on-resistance of the channel sufficiently low by increasing it to II@'. When such a large TFT i is used, the parasitic capacitance 25 becomes so large that it cannot be ignored, and the voltage drop ΔV mentioned above also becomes very large.

On the other hand, in order to extend the lifespan of liquid crystal materials, the liquid crystal layer is driven by alternating current. FIG. 4 schematically shows the principle of operation by this AC drive. Now, attention is paid to the tjth pixel circuit. The array line Xi turns on the transistor of the line at every time interval T4, and all the image signals of the data line Yj are stored in the capacitor 23. In order to drive the liquid crystal fully AC, the image signal voltage V (Yj) of the data line Yj is applied as shown in FIG. That is, in the display state (ON state), Vo[
volt], 0, vD[z volt], 0, the signal is '1'
Sent at 4 intervals and in synchronization with Dart Zorus ■ (Xt). In the opposite state (OFF state), the potential of the capacitor 23 changes as shown in [φi, j) in FIG.
For example, by setting the counter voltage Vc of the liquid crystal layer to VD/2, the desired display can be fully realized. However, v
The D/2 value needs to be larger than the threshold voltage of the liquid crystal layer. However, the actual potential φ of the capacitor 23
i, j change as φi, j shown in FIG. 4 due to the effect of the voltage drop ΔV mentioned above and leakage current of the switching transistor 21 or leakage DC of the liquid crystal layer. In the case of the example shown in Fig. 4, the potential VC of the counter electrode of the liquid crystal layer is set to V
It is clear that the desired operation cannot be achieved with D/2. For example, the VCC total ideal value D/2
ΔV.

In other words, Vc=Vo/2-ΔV
Even in the case of produces the effect of adding This is a problem for the longevity of liquid crystal materials, which is the purpose of AC operation. Furthermore, if the Δ■ value in the graph exceeds the threshold value of the liquid crystal in the OFF state, the display will no longer be in a completely OFF state, and the contrast of the entire display will drop sharply, making it difficult to obtain sufficient display custom orders. become unable.

Furthermore, it is necessary to obtain the ΔV value in advance, and depending on the value, it is necessary to apply a halfway potential to the counter electrode of the liquid crystal, which requires an extra circuit.

The above example shows the case of (l r Vo/2 + Vp) as an image signal, but for example -Vn/2, O, VD/2
(7) , j: ') A similar problem occurs even with a single signal peeking pressure.

[Purpose of the invention]

In view of the above points, the present invention extends the lifespan of the liquid crystal layer by eliminating the effects of voltage drop and leakage current that occur immediately after the 1 city 1 image signal '1 voltage is written in the capacitor that stores the image signal. Achieves almost perfect AC drive required for
The present invention provides a liquid crystal display device that enables highly reliable display without deterioration of contrast. 3. [Summary of the Invention] The present invention performs the above-mentioned AC drive using the entire transnosta matrix array. The basic structure is that the AC voltage applied to the liquid crystal changes symmetrically in positive and negative directions in the display state.

The outline of the present invention will be explained in detail with reference to the drawings. In the pixel circuit shown in Figure M2, the address line X1 now has a voltage of VG+Vao (Vc.

An image signal V(Yj) having a peak value VD is applied to the data line Yj in synchronization with the application of a signal V(X+) with a direct current bias. This capacitor 2
This image signal is accumulated in 3, and its terminal voltage is
The value becomes VD just before the voltage becomes vGo, and the electric charge Q- stored in the entire load capacitance including the capacitance 23 and the parasitic capacitance 25 at this time is Q--CBVn+Cp (Vo-Vc Vco
) ・Song --・Song・(1). C8p cP
2 respectively. ? , is the capacitance value of the parasitic capacitance 25. Here, vGo is smaller than the threshold voltage Vs that turns on the transistor, and VG +Vco
(/'i The value shall be greater than Vs. The effect of the DC cut capacitor 24 in FIG. 2 is not shown in equation (1), but the capacitance of this capacitor 24 and the liquid crystal 22 itself is It is obvious that it is included in the CS of equation (1).Next, Dart and Lus V (
Immediately after Xi) becomes Vco and the transistor 21 turns off, the total charge Q+ is 1 Q+ = Cs (Vn-Δv)0cP(vD-ΔV
Vco )=(2). Here, ΔV is the voltage drop M due to the parasitic capacitance 25 mentioned above. Since Q--Q+ (]), the voltage drop ΔV is given by equation (2).

In the present invention, the image signal voltage V of the data line Yj
(Yj), O and v in the display state as shown in FIG.
A repetitive voltage of D is applied, and a voltage of VD/2 is applied as a non-display state. At this time, the voltage applied to the opposite electrode of the liquid crystal is set to Vc''=0, and the direct pressure drop Δ in equation (3) is
The capacitance value Cpk of the dirt-drain parasitic capacitance 25 is set so that the V value becomes ΔVD/2. This condition is (
3) From the formula, it can be found as follows.

Here, the VD and vG values are uniquely determined from the transistor characteristics and the liquid crystal characteristics, and since C8 is also taken as large as the area allows so that it has sufficient retention characteristics, the CP value is uniquely determined. Sa2'L. If these conditions are set, as shown in FIG. 5, the AC 1 drive voltage φ1. j is completely symmetrical in terms of positive and negative.

〔Effect of the invention〕

FIG. 6 is a diagram for explaining the effect of the present invention using the transmittance-voltage characteristics of the entire liquid crystal layer. In the figure, Vth is the threshold voltage at which the liquid crystal layer starts to fully transmit. State A shows the most ideal operation when the voltage drop is Vo/2. In the figure, ○ indicates OFF state, × indicates ON state, and ○ in both positive and negative voltage regions indicates AC drive. Further, arrows in the figure indicate the effect of reducing accumulated charge due to leakage current or the like.

In the present invention, as shown in state B, even if the voltage drop ΔV is slightly smaller than VO/2, the effect is sufficiently reduced. That is, in B, no malfunction occurs in the display of ON and OFF states, and a display with a high contrast ratio can be obtained.

However, if the deviation is large, there is a risk of shortening the life of the liquid crystal layer, so the deviation of the ΔV value from the VD/2 value should be kept within approximately ±Vth/2 with respect to the threshold value Vth of the liquid crystal layer. It is desirable to do so. If the deviation is of this degree, it is possible to suppress the decrease in the life of the liquid crystal to some extent.

As described above, in the present invention, even if there is some leakage current in the transistor and liquid crystal layer of the pixel circuit,
It is possible to obtain ideal liquid crystal AC drive and high contrast display without display errors. Furthermore, since the opposing potential of the liquid crystal layer can also be fixed at zero, there is an advantage that no special power supply circuit is required.

Furthermore, since one end of the capacitor 23 is connected to the ground potential, address lines other than the address line of the pixel to which the capacitor 23 is connected can be used as a ground line, thereby increasing the degree of integration. You can also do it.

[Embodiments of the invention]

FIG. 7 is a sectional view of the main part structure of an embodiment according to the present invention.

The matrix array has 220 address lines and 0 data lines, and the address line spacing is 200 μm1.
The data line spacing is 250 μm. The transistor matrix array is formed on a glass substrate 71 using normal thin film integrated circuit technology. That is, an address line 72 which also serves as a gate electrode and a ground line is provided on the substrate 71.
(7zl, 72.,...) and 5i on top of this.
After depositing the 02 film 73, the amorphous Sl film 74 is deposited.
(741, 742-...) is deposited and patterned to form a data line ys (ysl e
752...) and a display electrode 76 that also serves as a drain voltage $i
(7el, 7e2.-)q is formed and covered again with a 5i02 film 77 to form a window on the display electrode 76. The display electrode 76 has a size of about 150×170 μm, and a liquid crystal layer 80 is provided on top of the display electrode 76, which is sealed with a glass substrate 78 provided with a transparent electrode 79. This transparent electrode 79 is biased to zero potential.

FIG. 8 shows the ftjth pixel circuit, in which 81 is a TFT made of an amorphous Si film 74. The display electrode 82 is configured with the display electrode 76 as one terminal electrode and the address line 72 adjacent to this pixel as the other terminal electrode. Kiya/? The capacitance value C8 of the capacitor 82 is approximately 3. Op
F is about 0.1 pF compared to the capacitance value C of the liquid crystal layer. Here, in this transistor matrix, as shown in FIG.
=20V'! Apply im. Transistor threshold value V
s is approximately 13 (V). On the other hand, the data signal on the data line Yj is in the ON state, repeating 0 and VD=1-OV, and in the OFF state, repeating 5 times. The capacitance value CP of the gate-drain parasitic capacitance 83 includes the channel capacitance when the transistor 81 is in the ON state (
4) According to the formula, approximately 1. It was set as OpF. As a result, the voltage μ applied to the liquid crystal layer 80 became as shown by φ++j in FIG. 9, and a nearly ideal AC drive was realized.

Note that when 20V is applied to the address line Xi, the adjacent address line X1-1 is at zero potential, so
Works as a grounding wire for the carrier and the seat 82. Father, when 20 (V) mark pO is applied to address line X1-1, φ1+J
The voltage becomes quite high, but this is instantaneous and poses no problem in operation.

FIG. 10 shows another embodiment according to the present invention, and similarly shows i-th and j-th pixel circuits. There are 20 address lines and 20 data lines each, and the matrix cell size is 1×IWa2. The difference between this embodiment and the previous embodiment is that no special capacitor is provided, and the capacitor 84 of the liquid crystal layer 80 is used instead. The matrix array was prototyped on a glass substrate using a common thin film integrated circuit manufacturing process, similar to the previous example shown in FIG.

Dart/Sorus total vG applied to address line = 15
v, 0.10゜o, io when the data line is ON
A signal of 5 [volts] is applied in the OFF state. Further, the potential of the counter electrode of the liquid crystal layer was set to 0. The value of the capacitance 84 of the liquid crystal layer 80 is approximately 3.2 pF, and from this, according to equation (4), the value of the gate-drain capacitance 83, including the channel capacitance in the ON state of the transistor, is approximately 1, 6 pF'e was provided. As a result, we were able to realize a nearly ideal AC drive and obtain a high-contrast display screen.

In the above embodiment, the voltage applied to the opposite transparent electrode of the liquid crystal is set to Vc''0, and the gate electrode of the transistor is
By setting the entire inter-drain capacitance to a predetermined value, the AC voltage applied to the liquid crystal layer was made to change symmetrically in positive and negative directions using an image signal that was a repetition of 0 and vD. However, the same effect can be obtained by modifying the dart pulse voltage and both signal voltages.

Therefore, the operating principle of another embodiment of the present invention will be explained with reference to FIG. The basic configuration of the pixel circuit is the same as in the previous embodiment. In this embodiment, a voltage V is applied to the opposite transparent electrode of the liquid crystal.
Apply Vc+Vcok as C+ dirt pulse 1Xi), and apply VC+ as image signal voltage V(Yj) in ON state.
A voltage of 4 is applied repeatedly to each field, and in the OFF state, VC + ΔV
Repeatedly apply the voltage. As a result, the first
As shown in Figure 1, "c'fr: As a reference, pressure is applied to AC 1 repeatedly of +Vz and -Vz in the ON state, and a voltage of zero in the ON state is applied, and the AC drive waveform can be made symmetrical between positive and negative. can.

Specific data according to this example will be explained.

The matrix array has 20 address lines and 20 data lines, and the address line interval is 1 inch and the data line interval is 1 inch. The basic structure of the transistor matrix array is similar to the previous embodiment. In this embodiment, a capacitor for storing image signals is not provided on the entire substrate, and the capacitor is replaced by the capacitance of the liquid crystal layer itself. The capacity of the liquid crystal layer is approximately 3.
It is 2 pF. The transistor matrix is always at zero level (ie, Voo=O) at address 2in, and 20 V (ie, vG=20) is applied only during switching. The threshold voltage Vs of the transistor is approximately 13 (V). The dirt-drain capacitance cp of the transistor, including the channel capacitance when the transistor is in the ON state, was about 0.29F. Therefore, when the voltage drop value is determined according to equation (3), it becomes ΔVΣ1.2 (V). Therefore, when the counter electrode potential of the liquid crystal layer is set to 'l<Vc-3.8 [volts] and the data line signal is set to 0110.
AC voltage of 0.10 [volt], 5 [volt] when in OFF state
Volt]. As a result, φ+ in Figure 12
As shown in pj, the liquid crystal layer was able to achieve almost ideal AC driving. In other words, when the display is in the ON state, an AC voltage of ±5V at the peak value can be applied to the liquid crystal, and in the OFF state, almost zero voltage can be applied to the liquid crystal, and the liquid crystal can be driven with high contrast and symmetrical positive and negative voltages. I was able to make it happen.

Note that the present invention is not limited to the above embodiments. For example, the semiconductor material for transistors is amorphous S.
Not limited to t, polycrystalline silicon may be used, and CdSe,
It may also be a semiconductor material such as CdB. However, in order to fully utilize the ρ effect of the present invention, it is not desirable for the switching transistor to be of a junction type (p-n separation).3. In AC driving, depending on the potential of the capacitor, the transistor turns on when it should be turned off, so it is desirable to appropriately adjust the bias potential Vaok to a value other than zero when the channel of the address line is turned off.

[Brief explanation of the drawing]

Figure 1 is an equivalent circuit diagram of a transistor matrix array.
Figure 2 is a diagram showing the pixel circuit of a liquid crystal display device using this matrix array, Figure 3 is a diagram showing the operating waveforms of the liquid crystal display device driven by DC drive, and Figure 4 is a diagram showing the operating waveforms by AC drive. 5 is a diagram showing operation waveforms of the liquid crystal display device according to the present invention due to AC driving, FIG. 6 is a diagram for explaining the effect thereof, and FIG. 7 is a diagram showing a liquid crystal display according to an embodiment of the present invention. 8 is a diagram showing the structure of the main part of the device, FIG. 8 is a diagram showing its pixel circuit, FIG. 9 is a diagram also showing its operating waveforms, FIG. 10 is a diagram showing a pixel circuit of another embodiment, and FIG.
12 is a diagram showing the principle operating waveforms of a liquid crystal display device according to another embodiment, and FIG. 12 is a diagram showing specific operating waveforms. 71...Glass substrate, 7. ? (7,?1,722...
・)・・・Address line (also gate electrode), 73...
・5i02 membrane, 74 (74+v74zy...)...
・Amorphous St film, 75 (75,,75,...)
・・・Data line (double electrode), 76 (761
, 76z...)...display electrode (also drain electrode),
77...5to2 film, 78...Glass substrate, 79...
...Transparent electrode, 80...Liquid crystal layer, 81...Thin film transistor, 82...Cano! Ship, 8,? ...parasitic capacitance between dirt and drain. Applicant's agent Patent attorney Suzu Ko Takehiko No. 2 [・1 '443 Figure G tlT t
i2 Fig. 4 Heat on cooking --- Me off state - No. 5! ! 1 6th N [B] o→--m-ni'=--4 1st 7th N 8th prisoner

Claims (8)

[Claims] (1) A plurality of address lines and data lines that are orthogonal to each other, switching transistors arranged at each intersection of these address lines and data lines, and whose sources and darts are connected to the data line and address rough-in, respectively, and each transistor. A liquid crystal display device consisting of a transistor matrix array formed by integrating capacitors with one end connected to the drain of the transistor and the other end grounded, and a transparent substrate having a transparent electrode facing the transistor matrix array. A liquid crystal display device which performs AC driving by alternately and continuously applying high-level and low-level signal voltages to the data line in a display state in synchronization with dart/gurus applied to the address line. 2. A liquid crystal display device according to claim 1, wherein the alternating current voltage applied to the liquid crystal changes symmetrically in positive and negative directions depending on the display state. (2) The liquid crystal display device according to claim 1, wherein the switching transistor is a thin film transistor. (3) The liquid crystal display device according to claim 1, wherein the capacitor is the capacitance of the liquid crystal itself. (4) The liquid crystal display device according to claim 1, wherein an address line other than the address line of the pixel to which this canopy 9th is connected is used as the ground line of the canopy 4th. (5) A plurality of address lines and data lines that are perpendicular to each other, switching transistors that are arranged at the intersections of these address lines and data lines, and whose sources and darts are connected to the data and address lines, respectively, and A liquid crystal display device consisting of a transistor matrix array formed by integrating capacitors with one end connected to the drain and the other end grounded, and a liquid crystal sealed between a transparent substrate having a transparent electrode facing the transistor matrix array. Vc, [:z] is applied to the opposite transparent electrode of the liquid crystal, and a voltage of Va [volts] is applied to the address line at all cycles, and in synchronization with this, the voltage is applied to the data line. In a liquid crystal display device that performs AC drive by alternately and continuously applying four signal voltages of VD (volts) and zero volts in the display state, vc = 0,
and a liquid crystal display device 1 characterized in that the capacitance value kcs of the capacitance is a capacitance value kcs of the switching transistor. (6) The liquid crystal display device 1 according to claim 5, wherein the switching transistor is a thin film transistor; (7) The liquid crystal display device according to claim 5, wherein the liquid crystal itself is used as the cover. (8) The liquid crystal display device according to claim 5, wherein an address line other than the address line of the pixel to which this capacitor is connected is used as the ground line of the capacitor.