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JPS59117244A - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS59117244A
JPS59117244A JP57226326A JP22632682A JPS59117244A JP S59117244 A JPS59117244 A JP S59117244A JP 57226326 A JP57226326 A JP 57226326A JP 22632682 A JP22632682 A JP 22632682A JP S59117244 A JPS59117244 A JP S59117244A
Authority
JP
Japan
Prior art keywords
heat sink
package
base
pellet
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57226326A
Other languages
Japanese (ja)
Inventor
Hisashi Yoshida
吉田　恒
Susumu Okikawa
進 沖川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP57226326A priority Critical patent/JPS59117244A/en
Publication of JPS59117244A publication Critical patent/JPS59117244A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はヒートシンクを有するパッケージを備えた半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device equipped with a package having a heat sink.

この種の半導体装［！ｉ（以下、ＩＣという。）として
、第１図に示すものと、第２図に示すものが考えられる
。This kind of semiconductor device [! As the IC (hereinafter referred to as IC), the one shown in FIG. 1 and the one shown in FIG. 2 can be considered.

第１図に示すＩＣは合成樹脂（以下、レジンという。）
を用いた非気密封止パッケージ１を備えている。このＩ
Ｃのペレット２は、ペレットとヒートシンク３との熱膨
張係数の差を吸収するためにヒートシンク３に溶着され
たモリブデン等からなる補助部材４に金・シリコン（Ａ
ｕ−８ｉ）共晶または銀（Ａｇ）ペースト接着によりボ
ンディングされており、このペレット２はリード５にボ
ンディングワイヤ６を介して電気的に接続されている。The IC shown in Figure 1 is made of synthetic resin (hereinafter referred to as resin).
A non-hermetically sealed package 1 is provided. This I
The pellet 2 of C has gold/silicon (A
u-8i) Bonded by eutectic or silver (Ag) paste adhesion, and this pellet 2 is electrically connected to the lead 5 via a bonding wire 6.

そして、この組立体はレジンモールドによりパッケージ
１に封止される。This assembly is then sealed into the package 1 using a resin mold.

第２図に示すＩＣは気密封止パッケージ１１を備えてい
る。このパッケージ１１はセラミックから形成されたベ
ース１２を備えており、このベース１２にはヒートシン
ク１３がメタライズ１４を介してあらかじめ溶着されて
いる。ペレット１５はヒートシンク１３にボンディング
され、ベース１２に形成されたり−ド１６にボンディン
グワイヤ１７を介して電気的に接続されている。そして
、ベレッ）１５を収容したベース１２のキャビティ部１
８はキャップ１９により気密封止されている。The IC shown in FIG. 2 includes a hermetically sealed package 11. This package 11 includes a base 12 made of ceramic, and a heat sink 13 is previously welded to the base 12 via a metallization layer 14. The pellet 15 is bonded to the heat sink 13 and electrically connected to the wire 16 formed on the base 12 via a bonding wire 17. The cavity portion 1 of the base 12 accommodates the beret 15.
8 is hermetically sealed with a cap 19.

しかしながら、このような従来のＩＣにあっては次のよ
うな欠点がある。However, such conventional ICs have the following drawbacks.

第１図に示すＩＣでは、レジンモールド工程がレジン利
用率や工数の面から多数同時処理を前提にしている関係
上、ヒートシンクの形状が長方形平板等単純な２次元構
造に限定されてしまい、また、ヒートシンクはリードフ
レームに仮止めしておく必要があるため、例えば小型で
４方から細いリードが近接して配線されているフラット
パックタイプパッケージ等に適用するのは困難であると
いう欠点がある。In the IC shown in Figure 1, the resin molding process assumes simultaneous processing of multiple units in terms of resin usage rate and man-hours, so the shape of the heat sink is limited to a simple two-dimensional structure such as a rectangular flat plate. However, since the heat sink needs to be temporarily fixed to the lead frame, it is difficult to apply it to, for example, a small flat pack type package in which thin leads are wired closely from four sides.

第２図に示すＩＣでは、セラミックでベースを形成する
際の焼結温度が１３００〜２０００ｔ：’の高温になる
ため、これに植設するヒートシンクは耐熱性に優れた材
料を使用することが必要になりコスト増を招来するとい
う欠点がある。In the IC shown in Figure 2, the sintering temperature when forming the ceramic base is as high as 1,300 to 2,000 tons, so the heat sink installed in it must be made of a material with excellent heat resistance. This has the disadvantage of increasing costs.

本発明の目的は、前記従来技術の欠点を解消し、放熱性
が良く、しかも安価なＩＣを提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and provide an IC that has good heat dissipation and is inexpensive.

以下、本発明を図面に示す実施例にしたがって説明する
。Hereinafter, the present invention will be explained according to embodiments shown in the drawings.

第３図は本発明によるＩＣの一実施例を示す縦断面図で
ある。FIG. 3 is a longitudinal sectional view showing an embodiment of an IC according to the present invention.

本実施例において、このＩＣのパッケージ２１はレジン
モールドにより一体成形されてなるベース部２２を備え
ており、このベース部２２はほぼ中央にキャビティ部２
３を有する平盤状に形成されている。このベース部２２
にはリードフレーム２４がキャビティ部２３に露呈する
内部リード２５と外部に突出する外部リード２６とを形
成するように植設されている。また、ベース部２２には
ヒートシンク２７がその一部なキャビティ部２３に露出
するように植設されており、このヒートシンク２７はベ
ース部２２にその一部を植え込まれた本体２８とこの本
体２８の外気突出部外周に嵌合される放熱フィン２９と
から構成されている。In this embodiment, the IC package 21 includes a base portion 22 integrally molded with a resin mold, and this base portion 22 has a cavity portion 2 approximately in the center.
It is formed in a flat plate shape with 3. This base part 22
A lead frame 24 is implanted to form an internal lead 25 exposed to the cavity portion 23 and an external lead 26 projecting to the outside. Further, a heat sink 27 is implanted in the base portion 22 so as to be exposed in a part of the cavity portion 23, and this heat sink 27 is connected to a main body 28, a part of which is implanted in the base portion 22. radiating fins 29 fitted to the outer periphery of the outside air protrusion.

ヒートシンク２７のキャビティ部２３での露出面にはベ
レット３０がＡｇペースト等導電性接着材による接着等
の適当な手段を用いてボンディングされており、このベ
レット３ｏは内部リード２５にポンディングワイヤ３１
を介して電気的に接続されている。A pellet 30 is bonded to the exposed surface of the cavity portion 23 of the heat sink 27 using an appropriate means such as adhesion using a conductive adhesive such as Ag paste, and this pellet 3o is bonded to the internal lead 25 by a bonding wire 31.
electrically connected via.

このようにしてベレット等を組込まれたベース部２２の
キャビティ部２３には気密封止部３２がレジンをボッテ
ィングまたはトランスファモールド等な用いてキャビテ
ィ部に充填することにより形成されている。In the cavity portion 23 of the base portion 22 in which the pellet or the like is incorporated in this manner, an airtight sealing portion 32 is formed by filling the cavity portion with resin using a method such as botting or transfer molding.

次に作用を説明する。Next, the action will be explained.

ベレット３０での発熱はペレット裏面を通してヒートシ
ンク２７０本体２８に伝達されてパッケージ２１の外部
に導出され、フィン２９により効果的に放出される。The heat generated by the pellet 30 is transmitted to the main body 28 of the heat sink 270 through the back surface of the pellet, led out to the outside of the package 21, and effectively released by the fins 29.

本実施例によれば、パッケージがレジンにより形成され
るので、パッケージがセラミックで形成される場合に比
べ安価に製作することができる。According to this embodiment, since the package is made of resin, it can be manufactured at a lower cost than when the package is made of ceramic.

すなわち、セラミックは１５００〜２０００Ｃの高温で
焼成されるが、レジンは１５０〜２００ｒの低温でモー
ルドされるため、パッケージのベース部に植込むヒート
シンクと仁ては高度の耐熱性は必要とせず、熱伝導性に
重点においた選定が可能になる。また、セラミック構造
の場合、気密封に面はメタライズ銀ろうまたは宇田付は
等が必要で、かつ多数箇所にこれを施す必要があり多大
の工数になるが、本実施例では気密封止部により封止が
行なわれ、この気密封止部はレジンモールドにより一回
で形成されるので、封止に必要な工数は最小で済む。In other words, ceramic is fired at a high temperature of 1500 to 2000C, but resin is molded at a low temperature of 150 to 200°C, so the heat sink embedded in the base of the package does not require a high degree of heat resistance. This allows selection with emphasis on conductivity. In addition, in the case of a ceramic structure, it is necessary to use metallized silver solder or udadsuke on the surface for air-tight sealing, and it is necessary to apply this to many places, which requires a large amount of man-hours, but in this example, the air-tight sealing part Sealing is performed, and since this hermetic seal is formed in one step with a resin mold, the number of man-hours required for sealing is minimal.

ヒートシンクは中間成形品ともいえるベース部に植え込
まれて一体成形されるので、最終製品ともいえる一括成
形パッケージに他の組立体であるベレット、リード、ボ
ンディングワイヤとともにヒートシンクが植設される第
１図で示した従来例＆ＣＪｔべ、ヒートシンクの形状の
自由度が大きくなり、放熱面積を大きくとった立体構造
のヒートシンクでもベースの成形時に植設させることが
できる。The heat sink is embedded in the base part, which can be called an intermediate molded product, and is integrally molded, so the heat sink is embedded in the final product, which can be called a one-shot molded package, along with other assemblies such as pellets, leads, and bonding wires as shown in Figure 1. Compared to the conventional example & CJt shown in , the degree of freedom in the shape of the heat sink is increased, and even a heat sink with a three-dimensional structure with a large heat dissipation area can be implanted at the time of molding the base.

なお、前記実施例では、ヒートシンクを本体とフィンと
の分割構造としたが、ヒートシンクは一体構造にしても
よい。In the above embodiments, the heat sink has a separate structure of the main body and the fins, but the heat sink may have an integral structure.

以上説明したように、本発明によれば、放熱性が良好で
、しかも安価なヒートシンク付きＩＣを得ることができ
る。As described above, according to the present invention, it is possible to obtain an IC with a heat sink that has good heat dissipation properties and is inexpensive.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例を示す縦断面図、 第２図は別の従来例を示す縦断面図、 第３図は本発明の一実施例を示す縦断面図である。 １．１１．２１・・・パッケージ、２２・・・ベース部
、２３・・・キャビティ部、２４・・・リードフレーム
、２７・・・ヒートシンク、３０・・・ベレット、３２
・・・気密封止部。 第　　１　　図 第２図 ／　／ 第　　３　　図 ７FIG. 1 is a vertical cross-sectional view showing a conventional example, FIG. 2 is a vertical cross-sectional view showing another conventional example, and FIG. 3 is a vertical cross-sectional view showing an embodiment of the present invention. 1.11.21...Package, 22...Base part, 23...Cavity part, 24...Lead frame, 27...Heat sink, 30...Bellet, 32
...Airtight sealing part. Figure 1 Figure 2/ / Figure 3 Figure 7

Claims (1)

【特許請求の範囲】[Claims] １、ヒートシンクな有するパッケージを備えた半導体装
置において、前記パッケージが、前記ヒートシンクの一
部が植え込まれ、そのヒートシンクに付設されたペレッ
トが収容されるキャビティ部を有するベース部と、前記
キャビティ部に充填されてなる気密封止部とを備えたこ
とを特徴とする半導体装置。1. A semiconductor device including a package having a heat sink, wherein the package includes a base part having a cavity part into which a part of the heat sink is implanted and a pellet attached to the heat sink is accommodated; What is claimed is: 1. A semiconductor device comprising: a hermetically sealed portion filled with air;
JP57226326A 1982-12-24 1982-12-24 semiconductor equipment Pending JPS59117244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57226326A JPS59117244A (en) 1982-12-24 1982-12-24 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226326A JPS59117244A (en) 1982-12-24 1982-12-24 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS59117244A true JPS59117244A (en) 1984-07-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP57226326A Pending JPS59117244A (en) 1982-12-24 1982-12-24 semiconductor equipment

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JP (1) JPS59117244A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6431443A (en) * 1987-07-27 1989-02-01 Nec Corp Semiconductor device
US5132776A (en) * 1988-10-28 1992-07-21 Sumitomo Electric Industries, Ltd. Member for carrying a semiconductor device
US5172301A (en) * 1991-10-08 1992-12-15 Lsi Logic Corporation Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5227663A (en) * 1989-12-19 1993-07-13 Lsi Logic Corporation Integral dam and heat sink for semiconductor device assembly
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5654587A (en) * 1993-07-15 1997-08-05 Lsi Logic Corporation Stackable heatsink structure for semiconductor devices
US5773886A (en) * 1993-07-15 1998-06-30 Lsi Logic Corporation System having stackable heat sink structures
CN102347290A (en) * 2011-09-30 2012-02-08 常熟市广大电器有限公司 Chip packaging structure with good heat dispersion property

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6431443A (en) * 1987-07-27 1989-02-01 Nec Corp Semiconductor device
US5132776A (en) * 1988-10-28 1992-07-21 Sumitomo Electric Industries, Ltd. Member for carrying a semiconductor device
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5227663A (en) * 1989-12-19 1993-07-13 Lsi Logic Corporation Integral dam and heat sink for semiconductor device assembly
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5172301A (en) * 1991-10-08 1992-12-15 Lsi Logic Corporation Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5654587A (en) * 1993-07-15 1997-08-05 Lsi Logic Corporation Stackable heatsink structure for semiconductor devices
US5773886A (en) * 1993-07-15 1998-06-30 Lsi Logic Corporation System having stackable heat sink structures
US5900670A (en) * 1993-07-15 1999-05-04 Lsi Logic Corporation Stackable heatsink structures for semiconductor devices
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
CN102347290A (en) * 2011-09-30 2012-02-08 常熟市广大电器有限公司 Chip packaging structure with good heat dispersion property

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