JPS59116987A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To lighten demands for the insulating film of a capacitor and to improve its reliability and yield of production in reading the charge accumulated in the accumulating capacitor by amplifying by a Tr for amplifying current in a cell and enabling to give a sufficiently large output signal to a bit line. CONSTITUTION:A n<+> type domain 6, which is a drain domain of a transfer transistor, uses a semiconductor substrate 12 as a collector, and it is also a base domain of an nnp bipolar transitor that uses a p type domain 7 that contacts a bit line 10 as an emitter. Accordingly, discharge of the charge in the accumulating capacitor Cm is controlled by the transfer transistor, and the drain current of the transfer transitor becomes the base current of the pnp bipolar transistor. The charge from the acumulating capacitor Cm flowed to p type domain functioning as is the base domain becomes current gain (hPE) times as much as the pnp bipolar transistor and gives an influence to the bit line 10. Accordingly, a large output is obtained as if the memory cell had a very large capacitor equivalently.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a random access memory (d-RAM) having a current gain inside the cell and increasing the amount of stored charge by the amount of the gain. The present invention relates to an improvement of a semiconductor memory device having the following.

Prior Art and Problems Traditionally, a d-RAM cell is a memory cell consisting of one switching transistor and one storage capacitor.
Many things are made up of cells.

The output voltage of this type of memory cell is read by dividing the charge of the storage capacitor by the bi-node line parasitic capacitance and the storage capacitance of the memory cell itself, so the output voltage is 1/1/1 of the power supply voltage. This results in a small value of 20 or less.

Therefore, in addition to requiring a highly sensitive sense amplifier,
During sensing operation, read data may be erroneously amplified due to noise signals mixed into the floating bit line. In recent years, a particular problem has been the generation of minority carriers due to alpha rays emitted from memory-mounted chips, which produce large noise components on bit lines.

Further, as the number of integrated bits of a memory increases, the number of cells connected to a bit line also tends to increase, so the bit line parasitic capacitance hardly decreases even as patterns become finer. In contrast, as the area of memory cells continues to shrink, storage capacitors must be able to store more charge per unit area;
It is inevitable that the dielectric film of a storage capacitor will become thinner and thinner. For this reason, the degree of integration of memories will eventually be limited by the limit in the thickness of the dielectric film of the storage capacitor. This thinness limit is the dielectric film (
This is a state in which the insulating film (insulating film) no longer exhibits an insulating effect due to carrier tunnels and rings. Specifically, this thickness is considered to be about 50 [people] if it is a silicon dioxide film.

Furthermore, prior to such physical limits, based on the statistical breakdown voltage distribution, in order to form an insulating film with good reliability, it is generally necessary to have a film thickness four times or more based on current manufacturing technology. is needed, and this limit is already approaching.

Purpose of the Invention The present invention amplifies stored data, especially when reading out the charge stored in a storage capacitor, using a current amplification transistor formed within the cell to provide a sufficiently large output signal to the bit line. This is intended to reduce the requirements for the insulating film of the storage capacitor.

Structure of the Invention In the present invention, a bipolar transistor for current amplification is provided in a memory cell in a semiconductor memory device, and when reading information, the electric current (data) accumulated in a storage capacitor is directly transferred to a bit line. A large output signal can be obtained by transferring a charge to the base of the bipolar transistor without any interference and extracting from the bi-node wire an amount of charge that is larger than the current gain of the bipolar transistor. Therefore, the memory cell according to the present invention has an apparently extremely large amount of accumulated charge.

Examples of the invention FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention.

In the figure, 1 is the gate electrode (word line R-WL) of the transfer transistor, 2 is the source region of the transfer transistor, n+ type region 3 is one electrode of the storage capacitor Cm, and 4 is the other electrode of the storage capacitor Cm. 5 is a dielectric film (insulating film), 6 is a drain region of a transfer transistor, n+ type region 7 is a p-type region formed within n+ type region 6, and 8 is a gate electrode of a write transfer transistor. (
write word line W-WL), 9 is the drain (or source) region of the write transfer transistor n+
A type region IO represents an aluminum bit line, 11 represents an insulating film, and 12 represents a semiconductor substrate.

In this embodiment, gate electrode 1. One electrode of the storage capacitor 3. Similarly, the other electrode 4 is made of, for example, a polycrystalline silicon film.

Electrode 3 is in contact with n1 type region 2, and electrode 4, which faces electrode 3 with dielectric film 5 in between, is connected to a suitable power source.

n+ type region 6 which is the drain region of the transfer transistor
It also serves as a base region of a pnp bipolar transistor having the semiconductor substrate 12 as a collector and the p-type region 7 in contact with the human line IO as an emitter. Therefore, the discharge (charging depending on how the voltage is applied) of the charge in the storage capacitor Cm is controlled by the transfer transistor, and the drain current of the transfer transistor is pnp.
This is the base current of the bipolar transistor. The charge from the storage capacitor Cm flowing into the p-type region 7, which is the base region, is applied to the bit line 10 by the current gain (h pe
), so that the memory cell is isometrically as if it had a large capacitor, and a large output can be obtained. The current gain of this bipolar transistor should be about 20 at the least.

A simple evaluation based on the above points shows that the storage capacitor in the semiconductor memory device of the present invention can be made 20 times thicker than the originally required thickness of the dielectric film. As described above, even if the limit of the thickness of the dielectric film as an insulating film is 50 [people], the thickness of the dielectric film 5 in the present invention is equivalent to 1000 [people].

Therefore, if this is made as thin as possible without sacrificing reliability, for example to 300 people, an output approximately three times that of a conventional memory cell will be obtained.

Now, in the semiconductor memory device of the present invention, since data reading from the memory cell is performed via the hyperbolar transistor as described above, the flow of data from the cell to the bit line 10 is unidirectional, unlike the conventional method. The cell does not have a function in which the hint line voltage is retransferred to the storage capacitor by performing a read operation and refresh is automatically performed. Therefore, in the semiconductor memory device of the present invention, a write transfer transistor having a gate electrode 8 and an n+ type region 9 which is a drain (or source') region is provided.

Normally, this writing transfer transistor is in an off state, but it is made conductive during writing or refreshing after reading to transfer the voltage of the bit line 10 to the storage capacitor Cm.

The write transfer transistor used here is unnecessary in a conventional memory cell, and this contributes to an increase in the area of the memory cell; In conventional semiconductor memory devices, this is the area where there is a thick insulating film for isolation from adjacent cells.
In the semiconductor memory device of the present invention, this is replaced by a transistor, and only the source and drain are isolated, and there is no significant increase in area. Rather, the advantage of obtaining a large-capacity and highly reliable semiconductor memory device is that the requirements regarding the thickness of the storage capacitor, especially the dielectric film, are relaxed.

Next, the operation of the memory cell described in connection with FIG. 1 will be explained with reference to FIGS. 2 and 3.

FIG. 2 is an equivalent circuit diagram of the embodiment of the present invention shown in FIG. 1, and the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.

In the figure, Ql has a gate connected to the read word line R-W.
Q2 is a bibonilla transistor whose emitter is connected to the bit line 10 and amplifies the current from the storage capacitor; Q3 is a write transfer transistor whose gate is driven by the write word line w-wL; N indicates a storage node of storage capacitor Cm, respectively. It should be noted that the storage capacitors C, m are connected to a suitable power source, for example a ground circuit. Further, if the transistor Q2 is used in common with adjacent cells, layout efficiency is improved.

3Fg is a timing chart showing the operation timing of the circuit shown in FIG. 2, and shows a case where writing is followed by holding, followed by reading, and refreshing.

"Reading operation" First, the storage node N of the storage capacitor Cm is connected to the ground potential (
V ss ). In the unselected cell, both transistors Q1 and Q3 are off, so the storage node is in a floating state. In the selected cell, the read word line R-WL is driven and the transistor Q1 is turned on. At this time, if the bit line 10 is bridged to a high level in advance, while the transistor Q1 is off, the base of the transistor Q2 is also in a floating state, but the entire bit line 1o is in a floating state. 1, transistor Q1 is turned on, and the charge on the bit line is transferred to the storage capacitor C through the base-emitter junction of transistor Q2 and the drain-source of transistor Q1.
m's storage node N is charged and its potential is raised. When the potential of the storage node N is Vs, the current flowing through the storage node N is VpC-△Vbl-Vbe-Vsh-Vss
...11). Here, VpC is the pre-charge voltage of the bit line 1°, which can generally be considered as the train side supply power supply voltage VOO. Also, △Vb
l is the voltage drop on the bit line 10 caused by reading. Further, Vbe is a forward voltage drop between the base and emitter of the transistor Q2, which is about 0.65 (V) when silicon is used as the material. Further, Vsh is the highest level voltage at the storage node N. From the initial state of reading until the formula tl+ is established, the amount of charge QIl that becomes the base current of the transistor Q2 is: QB = Cm (Vsh - V5s) ・□
... (represented as 21. Therefore, the charge QE amplified with the common emitter current amplification factor of the transistor Q2 as hpe (hp□-△1c/△IB) flows through the emitter of the transistor Q2. The charge Qε is ,QE=
(1+hpg) Cm (Vsh-Vss)・・
・ ・ (3) It can be expressed as: The parasitic capacitance of the bit line 10 is C,
If the voltage drop on the bit line 10 is △Vbl, then QE, -C-Il △Vbl ・
・ ・ ・(4). Also, the relationship between △Vbl and Vsh is expressed by equation (1), so from equations (3) and (4), ・ ・ ・ ・ (5) Solving this, it is expressed as (6) Ru.

As a specific example, if hFE = 20 Vpc = 5 (V) Cm / CB = 1 /30 Vbe = 0.65 (V), then from equation (6) △Vbl = 1.79, ■ [■
] can be obtained. If it is a conventional memory cell, 0.1613 (V) can be obtained as ΔVbl using a well-known calculation formula. If this is compared with the output of the memory cell of the present invention, the difference is obvious. Cm/Cwaichi 1/30
This ratio was an impractical value for conventional memory cells, but the present invention provides a sufficient output. vice versa,
If ΔVbl=0.5 (V) or so is sufficient, the required Cm/Cg can be 1/161.7 from equation (6). For example, if the bit line capacitance is 0.7 (pF), the storage capacitor Cm is 4.33 (fF) (f=10
-IJ. Assuming that the capacitor area is 10 μm 2 , a film thickness of 777 μm is sufficient for the storage capacitor Cm using a silicon dioxide film as a dielectric film. This value is
It will be appreciated how the memory cell of the present invention relaxes the requirements for storage capacitors, with film thicknesses that can be easily and reliably manufactured with current technology. If it is a conventional memory cell, △Vbl=0.5 (V)
In order to obtain this, Cm/CB = 1/9 is required for a storage capacitor with an area of 10 [μm2], and the thickness of the dielectric film is calculated to be 43.26 (people) for a silicon dioxide film. , which is not actually possible.

When reading data when the storage capacitor Cm holds a high level potential (#VDD), even if the 1-transistor Ql is conductive, almost no base current flows through the transistor Q2, so the bit line 10 is It maintains a high level of charge. Therefore, in the semiconductor memory device of the present invention, a large voltage difference can be obtained on the high node line IO corresponding to data "0" and "1".

"Refresh operation" After reading data from memory cell, storage capacitor Cm
It is necessary to transfer the voltage of the bit line 10 and perform refresh. That is, 0, because the memory cell in the present invention performs destructive reading. However, unlike the case of conventional memory cells, the destructive readout in the present invention does not mean that all the charge in the storage capacitor Cm disappears with -degree readout, and in some cases, multiple readouts may be performed. It is possible.

The reason for this is, as mentioned above, that the storage node N after reading
In this case, the potential has increased from the VSS level to Vsh, but since V sh<, V DD, there is still a potential difference at the storage node N with respect to the other data. Therefore, by recharging the bit line 10 to the ■DD level, reading can be performed. However, the output to the bit line 10 naturally decreases compared to the first read.

In any case, it is necessary to refresh the memory cell of the present invention. Refreshing is completed by turning on transistor Q3 and retransferring the voltage on bit line 10 to storage node N. The operation timing of the transistor Q3 does not need to be after the bit line 10 is driven to a sufficiently high or low level by the operation of the sense amplifier, but as soon as the transistor Q1 is made conductive and a signal is output to the bit line 10, the transistor Q3 is activated. may be made conductive. The reason for this is that the storage capacitor Cm does not have a very heavy load on the hint line, and by doing so, it takes a relatively long time (20 to 30 (ns)).
If the transfer gate for writing of transistor Q3 is driven within the operating timing of the sense amplifier that requires , and the refresh is completed immediately upon completion of the sensing operation, the time to drive the gate for writing will be within the operating timing of the sense amplifier. I hid inside. There is no delay in overall operating speed. Specifically, during writing, the gate of transistor Q3 is driven with a delay of about 20 (ns) relative to the gate of transistor Q1. The value of this operating time corresponds to the time it takes for the bit line 10 to be driven by the cell and for its voltage to fluctuate and reach a constant value.

"Write Operation" Writing is simply driving the gate of transistor Q3 to input data from bit cotton 10 into the storage note.

FIG. 4 is a block diagram of the main parts of the embodiment of the present invention including peripheral circuits. In the figure, 21 and 2
2 is a cell array, 23 and 24 are column decoders, 25 is a sense amplifier, 26 and 27 are row decoders, 28 is a word line pull-down signal input terminal, 29 and 3°0 are data buses, 31 is a data output huff circuit, 32 is a column address strobe (temperature) input terminal, 33 is a data output terminal, and 34 is a row address strobe (100) input terminal.
Strobe (RAS') signal input terminal, 35 read clock generation circuit, 36 delay circuit, 37 write enable (WE) signal input terminal, 38 write buffer circuit, 39 OR circuit, MC memory cell , D.M.C.
indicate dummy cells, respectively.

The peripheral circuits used in the present invention are almost the same as conventional ones.

However, the difference is that the write word line W-WL is driven with a slight delay after the read word line R-WL is driven. Although the cell size is somewhat larger in this respect, the cell output is extremely large compared to the conventional one, so a highly sensitive sense amplifier is not required, and as can be seen from the figure, a simple dynamic -Uses a type latch circuit. Therefore, the sense amplifier can be placed in a small pinch between the focus lines.

Effect of the invention The effects of the present invention are listed below.

■ Since there is a current amplification gain for the accumulated charge within the cell, the cell output is large even with a small capacitance.

■ A memo of the conventional one-island cell has a limit that is physically impossible depending on the lower limit of the thickness of the dielectric film of the storage capacitor, but according to the present invention, the thickness of the dielectric film can be adjusted to the lower limit. 2
The same effect can be obtained even if the thickness is increased to about 0 times, and in practice there is no restriction depending on the dielectric film thickness.

■ Since a storage capacitor with a much thicker dielectric film can achieve an output comparable to or higher than that of a conventional memory cell, its reliability and manufacturing yield will improve.

[Brief explanation of the drawing]

FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention, FIG. 2 is a circuit diagram of essential parts of an embodiment of the present invention, and FIG. 3 is a timing chart explaining the operation of the circuit shown in FIG. 2. , FIG. 4 is a block diagram of main parts for explaining a peripheral circuit applied to the present invention. In the figure, ■ is the gate electrode of the transfer transistor (word line R-WL), 2 is the source region of the transfer transistor, n+ type region 3 is one electrode of the storage capacitor Cll1, and 4 is the other electrode of the storage capacitor Cm. 5 is a dielectric film (insulating film), 6 is the drain region of the transfer transistor, n+ type region 7 is a p-type region formed within the n+ type region 6, and 8 is the gate electrode of the write transfer transistor. (Write word line W-WL), 9 is the drain (or source) region of the write transfer transistor n
The + type region 10 is an aluminum bit line, 1 is an insulating film, and 12 is a semiconductor substrate. Figure 1 Figure 2 Figure 3 Time - One glance

Claims (2)

[Claims] (1) In a semiconductor memory device having a memory cell consisting of a storage capacitor and a transfer transistor that charges and discharges charge in the storage capacitor when selected, the charging and discharging current of the storage capacitor is determined in the memory cell. 1. A semiconductor memory device comprising a bipolar transistor which amplifies the voltage and charges and discharges a human line charge with an emitter current. (2) One of the source region and the drain region of the transfer transistor is connected to a storage capacitor, and the other is formed as a common region with the base region of the bipolar transistor, and the bipolar transistor is formed in the common region. Claim 1, wherein the bit line is connected to an emitter region of
The semiconductor storage device described in 1.