JPS59114869A - Non-volatile semiconductor memory device having floating gate of polycrystalline silicon - Google Patents

Abstract

PURPOSE:To prevent such a defect that the threshold voltage of a parasitic MOS transistor decreases and shorten the manufacturing process by making the impurity doping into a floating gate the same type as in a semiconductor substrate. CONSTITUTION:An SiO2 film 2 as the first insulation film and a poly Si layer 13 serving as the floating gate are formed on the P type Si single crystal substrate 1, the ion implantation 12 of boron to adjust the threshold voltage a memory transistor is performed, and thus conductivity is given to the floating gate layer 13. An Si3N4 is formed as the second insulation film, a source, a drain, and a channel region are covered with a resist 10, the Si3N4 film 4 at a region to be etched is removed by etching, and the ion implantation 11 of boron to prevent a parasitic channel is performed. A field SiO2 film 5 is formed by thermal oxidation. An SiO2 film 9 is removed, and then a memory transistor is obtained in the same manner as the manufacture of a general EPROM.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a floating polysilicon layer.

(2) Description of conventional technology In recent years, there has been a strong demand for high-density integration of circuit elements in semiconductor devices.
ammable Read 0nly Memory (
Even in EPROMs, storage capacity is increasing as patterns become finer or cell structures change. The most commonly used type of EPROM at present is the nMOS type stacked-gate, which uses two-layer polysilicon technology, with the lower polysilicon layer formed in a floating type and used as a charge storage layer.
It is a type EFROM.

In addition to the above-mentioned method, a technique of forming a floating gate and a field insulating layer in a self-aligned manner has been proposed as a method for structurally further reducing the cell area. An outline of a method for manufacturing a memory cell using this new method will be briefly described with reference to FIGS. 1 to 3.

First, as shown in FIG. 1, a SiO2 film 2 is formed as a first insulating film on the surface of a Si single crystal substrate 1 (temporarily assumed to be P type), and then a polysilicon layer 3 is formed as a floating gate. Further, a Si, N, film 4 is formed as a second insulating film. After this, as shown in FIG. 2, the regions where the source, drain, and channel will be formed are covered with a photoresist 10, and a second insulating film 4 is formed using a plasma etching process or the like.
and floating gate 3 are sequentially and selectively and self-aligned removed. Using the second insulating film 4 whose shape has been determined in this way as a mask, as shown in FIG. An oxide film 5 is formed.

(This second insulating film 4 (843N4 film) is used not only as a mask for selective oxidation, but also as the second gate insulating film of the memory transistor.) A polysilicon layer that will become a control gate is formed on this second insulating film 4 (843N4 film). After that, the control gate is first patterned, and then the second gate insulating film and the floating gate are removed in a self-aligned manner with respect to the control gate, similar to the currently commonly used EFROM manufacturing method. Furthermore, source/drain regions are formed to form a memory transistor.

As mentioned above, BFROM using this new method
In this case, the cell area is structurally reduced by not only self-aligning the floating gate with the control gate in the length direction of the channel, but also self-aligning it in the width direction of the channel with a field oxide film. It makes it possible. Here, during the above-mentioned process, phosphorus is normally diffused into the polysilicon layer 3 which becomes the floating gate in order to impart conductivity. This is because the diffusion coefficient of phosphorus in S i 02, which is the first gate insulating film 2, is low, which prevents phosphorus, which is an impurity in the floating gate, from diffusing into the channel part even if it is subjected to heat treatment in a later process. This is because the threshold voltage of the memory transistor can be easily controlled.

However, as a drawback of the above process, the field oxide film 5
When forming the floating gate, a problem arises in that the impurity (phosphorous) in the floating gate diffuses to the outside (out-diffuse). As mentioned above, when forming a field oxide film, ions such as boron are implanted to prevent parasitic channels, but phosphorus is an opposite type impurity, so
This will contaminate the semiconductor surface or the inside of the oxidation device.

Furthermore, the following problems may arise from the above steps. In the above process, as shown in FIG. 2, the region where the source, drain, and channel will be formed is covered with photoresist, etc., and the second (insulating film 4 and floating gate 3 are removed in a self-aligned manner) However, in this case, the floating gate 3 is oxidized from the edge, resulting in a decrease in the channel width. Insulating film 4
One possible method is to form a field oxide film after removing only the floating gate, and oxidize the unremoved floating gate as it is, making it part of the field oxide film. However, in this method, impurities (phosphorus) in the floating gate At the same time as the above-described out-diffuse problem, the MOS transistors diffuse under the field oxide film and lower the threshold voltage of the parasitic MO transistor.

Such a problem is caused by the fact that the doping of the floating gate is of the opposite conductivity type to the impurity of the semiconductor substrate, for example, in the case of a P-type Si substrate, type 11 phosphorus is used for doping the floating gate. It was occurring in

3) Purpose of the invention The present invention eliminates the drawbacks of the conventional methods described above, based on the new experimental fact that the doping of the floating gate is the same type as that of the semiconductor substrate and does not impair the function of FROM even if it is at a low concentration. In order to do this, the floating gate is doped with the same type of impurity as the semiconductor substrate, and this allows doping of the semiconductor substrate with the same type of impurity as the substrate and doping of the floating gate in the same process. This made it possible to shorten the process.

(4) Description of structure and operation of the invention Two specific embodiments of the invention will be described below with reference to FIGS. 4 to 7. Although the n-channel polysilicon self-line type will be described for convenience of explanation, the present invention is not necessarily limited to the n-channel type, and may also be applied to the so-called polysilicon self-line type in which the floating gate is shaped in a self-aligned manner with the control gate.・There is no need to be a self-aligning type.

(Example 1) (1) First, as shown in FIG.
5in2 film 2 as the first insulating film at 300 ~
A polysilicon layer 13 is formed to a thickness of 100 OA, and then a polysilicon layer 13, which will become a floating gate, is formed to a thickness of 100 OA, for example, by vapor phase growth.
For example, boron ion implantation 12 is performed to adjust the threshold voltage of the memory transistor.
With 50 keys, it will be about 1.5 X I Q13Cm'. This ion implantation gives floating gate layer 13 electrical conductivity.

As shown in FIG. 5, the source, drain, and channel regions are covered with photoresist 10 or the like.
For example, by plasma etching in CF4+02, the 8 is N4 film 4 in the etched region is removed, and boron ions are implanted to prevent parasitic channels.
For example, at 100 kev I x 1019cm-2 or so.

(3) After removing the photoresist 10 by a suitable method, for example, in a lt-02 atmosphere (at 1000°C),
After 10 hours of thermal oxidation, the
A field 8i0z film 5 of about 1.5 μm is formed.

At this time, the 8 13 N4 film 4 serves as a mask for selective oxidation.
0 surface is oxidized to about 100~3008 to form 8i0z film 9
is formed. Also, in (2), photoresist 10
The portions of the polysilicon layer 13 that are not covered by the polysilicon layer 13 are oxidized during selective oxidation and become part of the field oxide film 5.

(4) After removing the 8i02 film 9 on the surface of the S l s N4 film, a memory transistor having a structure as shown in FIG. 7 is obtained in the same manner as the EPROM manufacturing method generally employed at present. That is, the polysilicon layer 6 that will become the control gate is formed to a thickness of, for example, 5000 Å, the channel region and the polysilicon wiring region are covered with photoresist, etc., and the control gate 6 and the second gate 5i3N4 film 4, floating gate 13,
The first gate 5IQz film 2 is sequentially removed in a self-aligned manner, and ions of, for example, phosphorus are implanted into the exposed substrate surface to form a source region 22 and a drain region 23.
Furthermore, after forming the interlayer insulating film 7, a contact hole 21 is made and an aluminum wiring 8 is provided, resulting in the process shown in FIG.

(Example 2) (1) First, as shown in FIG. 3, boron ions 12 are implanted into a P-type Si single crystal substrate 1 at a voltage of, for example, 70 keV to adjust the threshold voltage of the memory transistor.
A 5i02 film 2 is formed as a first insulating film to a thickness of 300 to 1000 Å, and a polysilicon layer 14, which will become a floating gate, is formed to a thickness of 100 OA, for example. (The polysilicon layer 14 is not yet made conductive.)

(2) Next, after forming a 51 g N4 film 4 as a second insulating film on this polysilicon layer 14 to a thickness of 500 to 100 OA, the source, drain, and channel regions are photo-etched as shown in FIG. Cover with a resist 10 or the like, remove Si, N, and film 4 in the region to be etched, and perform boron ion implantation 11 at, for example, 100K to prevent parasitic channels.
The ion-implanted polysilicon layer 14 is doped with boron to a certain extent during the subsequent heat treatment (field oxidation). The floating cathode 14 is doped with a low concentration and has conductivity.

(3) The subsequent steps are exactly the same as (3) and subsequent steps in (Embodiment 1).

(5) Description of Effects As is clear from the above examples, when the present invention is used, impurities in the floating gate diffuse out to the outside during field oxide film formation, damaging the semiconductor surface and the inside of the oxidation device. It is possible to prevent drawbacks such as contamination or diffusion under the field oxide film and lowering the threshold voltage of the parasitic MOS transistor;
This makes it possible to dope impurities into the floating gate in the same process as doping the inside of the semiconductor substrate with impurities of the same type as the substrate (adjusting the threshold voltage of memory transistors or adjusting the threshold voltage of parasitic MO8 transistors). The manufacturing process is stabilized and shortened at the same time.

[Brief explanation of the drawing]

FIGS. 1 to 3 show, in order of process, changes in the cross-sectional structure in the main steps in manufacturing an EPROM in which the floating cathode is formed in a self-aligned manner in all directions. FIG. 4 to FIG. 9 show the cross-sectional structure of the main steps of the embodiment of the present invention in the order of the steps. In the figure, 1... semiconductor substrate, 2...
...First Kate insulating film, 3.13.14...
・Floating gate, 4... ^... Second gate insulating film, 5.
...Field insulating film, 6...Control gate, 7...Interlayer insulating film, 8...Metal wiring, 9...Si3N4 film surface 5tO2 membrane, 1
0... Photoresist, 11... Impurity implanted portion for preventing parasitic channels, 12... Impurity implanted portion for adjusting threshold voltage of curved memory transistor, 21... Curved contact hole , 22...four source regions,
23...Drain region. Nai 7 Rope 2nd Figure Collection 3 Single 4. Concave /, ノ

Claims (1)

[Claims] A semiconductor substrate having a source/drain region, a polycrystalline silicon floating gate formed on this substrate via a first insulating film, and a control layer formed on the floating gate via a second insulating film. a gate, and a field insulating layer formed in a non-active region of the semiconductor substrate, the floating gate being formed so as not to overlap the field insulating layer, and the floating gate being formed in a non-active region of the semiconductor substrate. A nonvolatile semiconductor memory device characterized by having the same conductivity type.