JPS59114589A - Pattern writing control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [5] Technical Field of the Invention The present invention relates to a pattern writing circuit used in a display device having a multicolor graph display function.

[Technical background of the invention and its problems]

Conventionally, in a CRT display device with a graphic display function, the writing number to the video RAM is ``Read →
Each control of modification → writing is required (X).

That is, when turning on or off one dot on the coordinates, calculate the memory address where the dot exists by Jt,
Read the contents of that address (in units of 1-do from \ite or number), perform bit modification to turn on or off the bit corresponding to the above coordinates, and then convert the bit-modified data in units of byte or 1-do. Do not write to the same address as when reading above.

As described above, conventionally, writing display data to video RAM requires read, modify, and write controls, so control is required! Therefore, the burden placed on the software is large, and a lot of time is required for the writing process, which has been a major hindrance to improving the performance of this type of display system. In particular, in a so-called color graphic display device having a multi-color display function, it is necessary to provide video RAM for multiple sides (for example, 4 planes in the case of 16-color display), and the above-mentioned byte reading and processing are performed separately for each plane. Since bit modification, byte writing, etc. have to be performed, the various problems mentioned above have become more prominent. Furthermore, conventionally,
In the color graphic display device mentioned above, the graphics memory is used for one screen (plane) and 16 screens, for example.
8 kilobytes) and a 4-plane structure, CP
The address space for the above memory access seen from the U side requires 16 KB x 4 = 64 KB, and a lot of time is wasted in calculating addresses for each plane.

As described above, in conventional color graphic display devices, a large amount of time is consumed in the pattern writing process, which is a major hindrance to improving system performance.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pattern write control circuit that can speed up the process of writing patterns to a color graphics video RAM-M.

[Summary of the invention]

The present invention has a structure in which a plurality of video RAMs are simultaneously selected and specified in dye memory units, that is, plane units, and arbitrary patterns are simultaneously written in each of the video RAMs in the writing mechanism of a color graphics video RAM. Patterns for each ax color screen can be written to the video RAM at high speed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the overall configuration of an embodiment of the present invention. In the figure, 10 is a processing unit (hereinafter referred to as CPU) that controls the entire system, 20 is a CRT display circuit consisting of a color graphics video RAM using dynamic memory in a CRT display device, and its control unit, etc.; is CPU 10 and CR1
Address (AD) and data (DA) with display circuit 20
This is a CPU bus used for transferring TA), control signals (CTL), etc. 21 to 26 are CR1 display circuits 2
This is a functional circuit section that forms an internal component of 0. Here 21
is a color graphics video RAM (hereinafter referred to as V-RAM) composed of dynamic memory.
Here, 1 is used as a 4-sided (4-plane) MIJ structure.
Let us take as an example a case where six-color display is possible. Each of the four divided RAM planes is herein referred to as a ~'-RAM plane. Each V-RAM plane stores display dot data for a unique one-color screen, with each display dot representing one bit.
Since there are 200 0 dots and the pit width of the handled data is 8 bits, the total memory capacity is 16 KB (kilobyte), which is divided into 8 memory blocks (M, , M, ,...M,). 22 is C that controls the synchronization control of the CRT display section.
This is an RT display control unit (hereinafter referred to as CRT-C). 23
is the memory address (
MA) and C: Receive the processor address (PA) sent from PIJlo, select one of them,
This is an address selector (ADR=SEL) that outputs V-RAM address data (VRAD). 24
is a timing gate control unit (TIMG-CTL) that performs timing control for V-RAM access.
), a PIP/mask section for enabling bit modification on the V-RAM 21, and a color screen for simultaneously selecting and specifying one or more arbitrary color screens (V-RAM planes). It has a selection section, etc., the details of which will be described later. 25 is a quadruple data buffer unit (DAT'A-BUF) that simultaneously stores read/write data of the V-RAM 21 for each plane, and 26 is a V-RA
This shift register section (SHI FT-REG) also has a quadruple configuration and outputs the data read from M21 as a bit serial video signal (VID).

FIG. 2 is a block diagram showing in detail the configuration of the timing gate control section 24 shown in FIG. 1 above. In the figure,
201 is a wait control unit (WAIT-CTL) that performs timing control of V-R and AM access with cPUlo, and receives a memory request signal (MRQ) sent from the CPU 10 and controls the character clock (CH-CLK). ), the signal (WAIT) is held until the V-RAM access is completed.
is sent to the CPU 10. 202 HAV-RAM
It is a timing generator (TEM-GEN) that generates various control signal trays for the
Memory write request signal (MWR) sent from PU10
), and also receives the character clock (CH-CLK)
, an address select signal (SEL), a column address select signal (CAS), an address select signal (RAS), and a write enable signal (WE). 203 is a decoder (D, EC) that receives and decodes the port address (PORT-ADR') sent from CPUIO;
BMR is a mask register strobe signal 5-psR obtained by this decoder 203 and is a plane select register strobe signal.

204 specifies and acts on each plane of the V-RAM 21 only on arbitrary bits. , V-RAM2
205 is a hit mask section to enable modification on the V-RAM 21.
- This is a color screen selection unit for simultaneously selecting and specifying an arbitrary number of RAM planes. Here, by selectively supplying a column address select signal (CAS) to four V-RAM planes, any one to It is configured to selectively permit/prohibit access to four specified planes.

FIG. 3 is a block diagram showing in detail the configuration of the V=RAM peripheral section in FIG. 2 above. As mentioned above, the V-RAM 21 has V-RAM frames 21A' and 21A', which correspond to four color screens each consisting of 16KB.
B, 21C, 21DklJ: Consists of. Here, it is the V-RAM plane 21A.

218.2IC is R (Red), G (Green
).

The dot pattern information for each screen of B (Blue) is stored separately, and the V-'RAM plane 21D stores the luminance information (full gradation/half gradation) of each display dot, resulting in a total of 16 color dots. Let's take as an example a case where patterns can be displayed. Each of these V-RAM brains 21A, 21B, 21G
, 21D are given the V-RAM address data (VΔRP> output from the 71' L/s selector 23 in common, and are accessed simultaneously by the same address. Therefore, the V-RAM address data handled here
The address space for M access is 16 KB, and the address bit width is 14 bits (7 bits x 2). Also, V-RAM7L/-n 21A, 21B.

Corresponding to 21G and 21D, the data buffer section 25, shift register section 26, and data bus (LOCAL-BUS) between the V-RAM and the data buffer section are 4 each.
25A for heavy duty.

25B, 25C, 2, 5D are V-RAM planes 21
Plain data buffers, 26A, 26B, 26C, corresponding to A, 21E3.21'C,, 210.

26D is 1ilL; V RAM'7L/-21A
, 21B, 2IC, and 21D. 301, 302. . . . are constituent elements of the bit mask section 204, and 301 is C.
I) Bit mask data (BMD) sent from UIO
) receiving the bit mask register (BI T-MAS)
302, 302, . . . are gates that output each bit output of the bit mask register 301 at a timing according to the write enable signal (WE). Each of these gates 302, 302. ... Each V-RAM brain 21 of the write RAM 21 output from
Commonly given to A, 218.2IC,, 21D. 4
01, 402, .
G>. 402, 402°... are each bit output of the plane select register 401 (PSo, PS, .
PS, , PS3) respectively and commonly receive a column address select signal (CAS),
The corresponding bit output of the plane select register 401 is “
1', column address select signals (CASA, CASB, CASc) for the corresponding plane.

This is a gate that outputs CASD). This gate 40
2.4-02. The output of ... is the corresponding ■-R
It is supplied to AM planes 21A, 218.2IC, and 21D.

FIG. 4 is a circuit block diagram specifically showing the configuration of the V-RAM 21. Here, each V-RAM brain 21A
, 21B, 21C', 21D are 8 memory blocks of 16 bits each (Mo-M7, M, o-Mo,
+M2o"-, M2.+M3o-M3□). Therefore, each V-RAM plane 21A,
21B, 21c, 21D are each 1'6K
B 4 training - and the entire V-RAM21 is 64KB
It becomes the composition. V-RAM address data (VARD) is transferred to each V-RAM via address line VRA-VRA.
7L/- pin 6 21A, 218.2IC, 21D in common, each V-RAM plane 21A, 21'B;
All addresses 21G and 21D are commonly addressed.

In addition, the row address select signal (RAS) is
M-brane 21'A.

Column address select signals (CASA, CASs, CASc) are commonly applied to 218.2IC and 21D and output from the color screen selection section 205'.

CASD) are the corresponding V-RAM planes 21
A, 21. B, 21c, 21D are given separately.

The lie output from the bit mask section 204 is
It is commonly given to AM branes 21A, 21B, and 210.21D with corresponding bit positions (corresponding memory blocks).

FIG. 5 conceptually shows a V-RAM write access control mechanism according to an embodiment of the present invention. Each V-RAM brain 21A.

21B, 2IC, and 21D are simultaneously and selectively controlled for write access by the bit selection function of the output mask section 2Q4 and the plane selection function of the color screen selection section 205.

The operation of one embodiment will now be described with reference to FIGS. 1 to 5. Access to the V-RAM 21 of the CRT display circuit 20 is selectively performed by the CPU 10 and the CRT-022. At the timing when the CR7 screen is refreshed in normal times, the address select signal (SEL) generated by the timing generator 202 of the timing gate control section 24 is sent to the CRT-C22.
Therefore, this memory address (MA) is selected by the address selector 23, and the V-RAM address data (VRAD) is selected.
As each V-RAM'M play of V-RAM21,
A, 21B.

Commonly given to 21C and 21'D. In this case, V-
RAM 21J: Plane shift register 21A to which the four types of display dots I to 1 for each color screen that have been read out correspond, respectively, in the shift register section 26.

After being loaded into 21B, '2IC, and 21D, they are shifted out and bit serial video signals (VI
D) is sent to the CRT display section.

On the other hand, the V-' RAM access request from CPU10 is sent to the wait control unit 201 of the timing gate control unit 24 by a memory request signal (MRQ
) is given.

At this time, the processor 1 address (PA) is supplied as a memory address to the V-RAM 21, and furthermore, the write data is sent to each of the data buffer sections 25.

Plain data Baranoa 25A, 25B, '2.5C.

25D, or 'read data is guided to the CPU bus 30 via the data buffer section 25. These operations are performed based on the signal ψ output from the timing gate control section 24. The weight control section 201 of the timing gate control section 24 is C'
A wait signal (WEIT) is sent to the PU 10 until the memory access of the V-RAM 21 is completed.In addition, the timing generator 202 of the timing gate control unit 24 outputs an address when the CPU 10 can access the V-RAM. For the selector 23,
Outputs an address select signal (SEL) with contents for selecting and specifying a processor address (PA). Further, the timing gate control unit 24 outputs a row address select signal (RAS) for controlling the V-RAM 21;
Outputs column address select signal (CAS), write enable signal (WE), etc. Of these signals,
Row address select signal (RAS) remains V-R
AM21 (7) Each V-RAM7L/-n 21A, 21B
, 21C, and 21D, and the column address select signal (CAS) is sent to the V-RAM plane 21A after passing through the color screen selection section 205.

Column address select signals (CASA, CASB, CASc) corresponding to 21B, 21G, and 21D.

CASD) as each V-RAM21 of the V-RAM21.
A, 21B, 21C, and 21D are individually supplied. or,
The write enable signal (WE> is applied to the v-RAM when a memory write request (MWR) is generated from the CPU10 and a C'PU access is made to the V-RAM21.
2.1 is output at the required timing and supplied to the bit mask unit 204. The bit mask register 301 of the P1-mask unit 204 is defined as one address register from the perspective of the CPU 10, and can be set to any value. receives the bit mask register strobe signal (S-BMR) output from the decoder 203 and latches 8-bit bit mask data (BMD).

The above write enable signal (WE) is transmitted to each output gate 302, 302, . . . of the bit mask register 301.
This write enable signal (WE
”), the V-RAM planes 21A, 2'IB, 2IC, 2ID corresponding to the bit set in the bit mask register 301 (bit in "1" state)
A write enable signal (WEi) is output only to the upper bit position, that is, the memory block (Mi). By doing this, writing to each V-RAM plane 21A, 21B, 210.21D of the V-RAM 21 is performed as follows.
This can be done only for desired bits. For example, V selected by the color screen selection unit 205, which will be described in detail later,
-RAM plane 21A.

When a request to turn on only bit 3 of an address consisting of 21B and 21B occurs, after setting the binary value ``00001000'' to the bit mask register 301, all ``1'' (data ``F'' F
This can be achieved by simply writing ``H]1Cx).Also, if a request to turn off only bit 3 of that address occurs, all ``O''(data',``-OQ'' HE
This can be achieved by simply writing Also, multiple bits of the bit mask register 301 are turned on, and the color screen selection section 2
For example, V-R, AM plane 21A by 05.

21B, 21C, are selected, the V-RAM plane 21A, which corresponds to each turned-on bit,
Each bit value of 21B and 21C is to be rewritten. Also, if access to bye 1 (or word access) is required, this is accomplished by letting all bits in the bit mask register 301. By using such a bit mask means, the bit to be modified J can be arbitrarily specified.

Next, the operation of the color screen selection section 20 will be explained. The color screen selection unit 205, like the bit mask unit 204 described above, uses the V-RAM! When accessing data, data sent from the CPU 10 as necessary (
PSD), and only the V-RAM plane specified by the data (PSD) can be accessed for writing. That is, the plane select register 401 of the color screen selection unit 205 receives the plane select register strobe signal (S-PSR) output from the decoder 203 according to the port address (PORT-A[)R) from the CPU 10, and selects the plane select register strobe signal (S-PSR) from the CPU i. Latch the 4-bit plane select data (PSD) sent from o. Each bit output (PS, PS, F) S, PS of this plane select register 205
) are the corresponding output gates 402; 402.
... is supplied to one input terminal of the gates 402, 40.
2. The above-mentioned column address select signal (CAS) is commonly applied to the other input terminal of . Therefore, when the color screen selection unit 205 receives the plane select data (PSD) and then the column address select signals (CA, S), the color screen selection unit 205 selects the output gate 402 according to the contents of the data (PSD) set in the plane select register 205. ，
402. ..., column address select signals (CASA, CAS, B) specific to the corresponding plane.
, C.A.Sc.

CASD). For example, the plane select register 205 includes the V-RAM plane 21A.

In order to select 21B and 21C, only the bit output PSo is set to 0'', and the other bit outputs (PS+ = PS3) are set to 1''.
When the column address select signal (CAS="1") is generated after Qo - "11 '10") is set, the signal is input only from the gate 402 which receives "1" from the plane select register 205. A column address of 1 level, that is, 110 II level is output. Output gates 402, 402 . ,
...Column address select signal (C
ASA, CASB.

CASc) is the corresponding V-RAM plane 2
．． 1A, 21B, and 21C, and among the V-RAM planes 21A, 218.2IC, and 21D, each plane 21A and 21821G except 21D can be accessed for writing at the same time.

As described above, each V-RAM plane 21A.

In 21B, 2IC, and 21D, write bits are specified by the P1-mask unit 204, a color screen (plane) is selected by the color screen selection unit 205, and the write bit is specified for the specified bit position of the selected plane. , dot patterns are written simultaneously.

Here, the bit mask section 2o4. An example of writing a pattern into the V-RAM 21 using each function of the color screen selection section 205 will be explained.

First, when clearing the screen according to a software request, the CPU 10 writes all "0°' to the entire screen area of the V-RAM 21 (7). At this time, the bit mask register 301 of the bit mask unit 204 is set to As described above, bit mask data (BMD
;11111111") is set, and the color screen selection section 2
The plane select register 401 of 05 has the same a
ll “1” plane select data (PSD;
"'1111") is set. Also, write data of a11'0' is stored in the plane data buffers 25A, 258.25G, and 25D, respectively. As a result, each output gate 302.3 of the bit mask section 204
02. ..., all outputs are set to 0 according to the write enable signal (WE) to permit writing of all 8 bits.
From each output gate 402, 402, . Signal (CAS A, CASB, CAS c.

CASD) is output. Bit mask part 2 like this
By specifying the filtering bit in 04 and selecting the internal plane in the color screen selection section 205, each V-RA, M plane 2
By writing to all addresses 1A, 2'lB, and 210.21D with an address common to each plane,
Each V-RAM plane 21A, 21B, 2” IC, 2
1D is simultaneously controlled to write "o" in byte units, that is, to clear the screen.

Furthermore, even when filling in a specific color, high-speed writing can be performed by performing screen clearing in substantially the same manner as described above.

Furthermore, when a dot pattern of a specific color is selectively displayed at a specific position on the screen according to a software request, the CPU 10 calculates the processor address (PA) and bit position corresponding to that position. , bit mask data (BMD) having a bit pattern configuration in which the bit position is “1” is set in the bit mask register 301 of the bit mask unit 204. Furthermore, a color screen selection section 205
The plane select data (PSD) corresponding to the specified color is set in the plane select register 401 of the controller 401, and then all "1" is written to the corresponding address (PA). With this, only for any position with the screen,
Write a dot pattern in any color. Also, if you want to clear the color at the position on the screen, set the data in the bit mask register 301 in the same way as above, and set the plane select data (PSD,) of all "1" in the plane select register 401. , all "O" may be written to the address corresponding to the specified position.

By controlling the pattern writing to the V-RAM 21 as described above, any plurality of color screens, that is, any plurality of V-RAs.
Since patterns of arbitrary colors can be controlled to be written to the M planes 21A, 21B, 21G, and 21D at the same time, color patterns can be written at high speed. Also, C
Since the PU 10 can handle all the color screens (four planes in the above embodiment) in a superimposed state, it can control access to the V-RAM 21 while greatly enlarging the address space.

〔Effect of the invention〕

As described in detail above, according to the present invention, the video R
A color screen selection means for simultaneously selecting and specifying a plurality of AMs in color screen units, that is, plane units, is provided, and an arbitrary pattern is simultaneously written in each of the plurality of planes specified by the color screen selection means. By doing this,
Pattern writing processing to the video RAM can be performed at high speed.

[Brief Description of the Drawings] Fig. 1 is a block diagram of one embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of the timing gate control section in the above embodiment, and Fig. 3 is a block diagram showing the configuration of the timing gate control section in the above embodiment.
-A block diagram that does not show the configuration of the RAM peripheral part; FIG. 4 is a circuit block diagram showing the configuration of the V-RAM in the above embodiment; and FIG. 5 is a diagram conceptually showing the write access control mechanism in the above embodiment. It is. 10... place J [ii'fl (CPLI), 20.
C'RT display circuit, 21...Video R, AM (V-
RAM), 21A, 21B, 21C, 21D・V
-RAM7L/-, 22 ・CRT display control unit (CR
T-c), 23...Address selector (ADR-'5
EL), 24...Timing gate control section (
T'1M・G-CTL), 2.5...Data buffer section (DATA-BUF), 26 shift register section (
S l-11F T-REG), 30...C
I) U bus, 201... Way 1-control unit (WAIT-CTL), 202... Timing generator (TIM-〇EN), 203... Boat address decoder (DEC), 204... Bit Mask section, 205... Color screen selection section, 301... Bit mask register (BIT-MASK...REG), 30
2゜302...402...Gate, 401.
...plane select register, MRQ...memory refresh I~ signal, WAIT...wait signal, MWR...
・Memory write request signal, CH-CL'K...Character clock, SEL...Address select signal, C
AS...Column address select signal, RAS...
Row address select signal, WOE...Write enable signal...S-BMR...Bit mask register strobe signal, 5-PSR...Plane select register strobe signal, BMD...Bit mask data, PSD...・・Plane select data, VID・・
・Video signal. Figure 1 0 CPU-BLJS

Claims (1)

[Claims] (1) a graphics memory composed of a plurality of memory planes each storing a plurality of pigment information for multicolor display; means for supplying common address information to address input terminals of each of the memory planes; means for supplying common old write data to data input terminals of memory planes; a plane selection register in which memory plane selection information is set prior to supplying the common address information and write data; the address information; , a circuit that supplies an access permission/inhibition signal for the memory plane to a control terminal of the memory plane specified by the selection information set in the plane selection register when write data is supplied, and the access permission /A pattern write control circuit characterized in that the write data is written in common to a storage location specified by the address information in a memory plane to which access is permitted by a prohibition signal. ('2J) The storage location of each memory plane specified by the address information is composed of multiple bits,
Claim 1, characterized in that means is provided for writing data for each of the plurality of bits, and the means and the inhibition signal output circuit write and access any bit of any memory plane. The pattern writing control circuit described.