JPS59113621A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a breaking at a stage of an electrode on the formation of the electrode by selectively removing a first silicon oxide film to expose one part of the surface, doping an impurity to the surface of the first silicon oxide film to form a protective film and forming a second silicon oxide film on the protective film. CONSTITUTION:The silicon oxide films 14 used as masks for diffusion for forming P type high impurity concentration regions 4 and 5 are left, and masks for diffusion by the films 14 are formed newly and an N type upper gate region 6 and N type regions 12 are formed while P-N junctions 13 are formed among the P type regions 4 or 5 and the N type regions 12. Phosphorus for passivation is diffused simultaneously to the silicon oxide films 14, and PSG films 15 are formed to the surfaces of the films 14. The silicon oxide film 16 is formed on the whole surface through CVD. When forming electrode extracting windows 7, 8, eaves are not formed on the N type regions because the end sections of the PSG films terminate on the surfaces of the N type regions 12 and are coated with the silicon oxide film 16 and are not exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for discharging a semiconductor device, and more particularly to preventing breakage of an electrode at a stepped portion of an insulating film. Phosphorus siligate glass (f'SG) has been well known as a passivation material for devices. Pe(
JD is widely used as a passivation agent because it has getter seedlings and glock seedlings containing ionic impurities such as sodium chloride (Na+) and can be formed relatively easily.

・Changing Figures 1(a) to te), a conventional P-channel junction type infant transistor (hereinafter referred to as J-F l
Pa (referred to as ti T) as a passivation odor.
), the case where 1g is used will be explained.

First, as shown in FIG. 1(a), an n-type semiconductor substrate (P-type epitaxially grown on υ) which becomes the gate of the F section (tti)
(2) is formed. As shown in FIG. 1(b), in order to improve the ohmic properties of the thin source and drain electrodes formed with the n-type separated head (3), the P-type sieve impurity region (4) and ( 5) is shaped by the impure proboscis expansion method.

Here, (14) is P-type Karasu impurity +127 once subterranean <4
) (5) A diffusion mask made of a silicon oxide film is used for the remainder of the process. As shown in FIG. 1(C), the n-type upper gate head (6) is removed by spreading and removing impurities. Subsequently, the remaining P-type epitaxial rm L is formed on the silicon thickening layer (14) for the expansion mask.
2) The surface of 2) is thermally oxidized to form a shielding silicon oxide film (14), and a passivation paste is applied to the entire surface of this silicon oxide film to create a PSGI viewer (15). A silicone acid pattern (16) is broken by CVD. Here, i S Ga (15) has hygroscopicity along with ionic impurities and the getter effect of the song, but if the PBG film is left on the surface of the element, the moisture resistance of the element will deteriorate, so phosphorus is removed. Pure silicon oxide free
It has a sandwich structure of PSG', d which covers a large area of CPSGJ.Next, as shown in FIG. ) is opened on the P-type high impurity non-uniformity region (4) (5). Next, as shown in Figure 1 (θ), the source electrode (9), the drain electrode (1o) and the semiconductor substrate (1) side are opened. The target P-channel J by tearing the gate electrode (11)
-B" B T can be changed to I"4.

In devices manufactured by such a manufacturing method, when opening the source and drain electrode formation e (7) L8), the PBG) is more difficult to form than a silicon oxide film which is a 1-a layer.
Because the etching speed is fast, the K P S G j pattern is etched deeply in the yellow direction as shown in Figure 2 (a), resulting in silicon oxidation! 18) is formed. When polarization (9) is formed on top of this, 4
The poles may be disconnected, or even if they are connected at the initial stage, they may be severely damaged as shown in Figure 2(b)18)
The electrode (9) is turned up due to thermal strain or strain during molding, and the electrode (9) is cut, causing a break in the electrode.

If the electrodes do not overlap the eaves, there is no 4'a, but in the case of semiconductor devices or integrated circuit devices with sideways overlays that overlap the eaves, electrode breaks occur due to the steps in the eaves, so PSG is used. The sand inch structure passivation had the disadvantage that it could not be used as it was.

The invention was made in view of these drawbacks, and by selectively removing the first silicon oxide film and exposing a part of the surface of the semiconductor substrate, impurities were added to the surface of the $1 silicon oxide film. J
The present invention provides a method for manufacturing a semiconductor device in which step breakage during electrode formation is prevented by forming a protective layer by tongs.

P-channel Jk', which is an embodiment of the present invention, will be described below.
FiT will be explained in detail with reference to Figures 3 (a) to (e).

'l'ffJa As shown in figure (a), n becomes the do part gate.
A P-type evixaxial growth layer (2) is formed on a P-type semiconductor substrate (1). As shown in Figure 3 (b) on the arrow -J (n
After forming the la region (3), a P-type high impurity impurity (a degree) was added (
4) and (5) are formed. Note that this 1-silicon oxide film (14) is used as a diffusion mask, but this silicon oxide film (14) is left as is. Next, a new diffusion mask made of a silicon oxide film (14) as shown in FIG. Proboscis region (4
) (5), and at the same time form a PN junction (13) in the P shadow region (4) and the n-shape head (12). At this time, the upper gate region (6) and n
If it is not possible to form the shadow region (12) at the same time, first cut out the gate region (6) and then deposit silicon oxide on the gate region (6) to form the window for forming the n shadow region (12). Even if you open it, it will not work.

Also, at the same time as the formation of the n-type head (12), silicon e
Phosphorus diffusion for passivation is performed on the chemical tb (14), and a PBG film (15) is formed on this surface. After that, as shown in FIG. 3(d), a silicon oxide film (16) is formed using CVi over the entire main surface of the device. At this time, n shadow areas (1
2) No PBG pattern is formed on the top, and only a silicon oxide layer (16) is formed on the 0th order in Figure 3 (θ
) as shown in the source and drain electrode outlet (
7).
P shadow area (4) (5) respectively so as not to reach 5)
and a source electrode (9) after opening in a part of the n shadow area (12).
), the drain magnetic pole (10) and the gate electrode (11) can be broken to obtain the desired P-channel sea fl'ET.

In addition, according to this manufacturing method, which shows a pattern diagram of an embodiment of the invention in FIG. 4, electrode extraction windows (7) (8)
The edge of the f'sG film terminates on the surface of the n-shaded region (12), and this part is covered with silicon oxide (16) and is not exposed. , the silicon oxide film on the n-shaded area is not shaded, and the electrode is prevented from breaking in this area. On the other hand n
Since the shaped region (12) is formed shallower than the P-shaped head (4) (5), it is floating within the P-shaped region (4) (5), and the source electrode (9) and drain electrode(
10) does not affect the characteristics of the device.

In addition, if the passivation film breaks on the upper gate region (6), the P-type epitaxial layer (2), and the gate junction (17), the passivation effect is sufficient, and the P-type high impurity degree region ( 4) Even if a part of (5) and the n-shaded area (12) are not covered, the characteristics of the element are not affected at all.

As described above, a P-channel J- according to an embodiment of the present invention
F' W T K p has a getter young fruit and a passivation effect, and it is easy to form a type 1 rice (PSL)
Even if JD is used as a passivation film, the structure is such that no eaves of the insulating film are formed, which causes breakage at the stepped portions of the electrode insulation. It is possible to obtain a high-quality, low-definition element without the need to add .

In the above embodiment, the case where it is applied to P-channel J-k' t T was explained, but it is also possible to apply
It can be used for d in bipolar transistors.

In addition, when k'B, IIJ (15) 'k, for example, is replaced with a boron silicate glass model (j3sG), similar young fruits are produced.

According to the present invention, the first silicon oxide film is selectively removed to expose a part of the surface of the semicircular substrate, and the surface of the first silicon oxide film is coated with an impurity to form a protective film. A second silicon oxide film is formed on the edge of the protective layer, and then the surface of the conductor substrate is removed without removing the protective layer.
4, and a pole pole is formed on this exposed surface, which prevents the electrode from breaking when forming the electrode, which is a problem.

[Brief explanation of the drawing]

Figures 1(a) to (e) show the conventional P-channel/l/J
-F Jii T manufacturing method sectional view by process, 2nd
Figure ta) (b) is a cross-sectional view showing the eaves of the silicon oxide model formed on the step part of the rim of J-F BON T (DI!!3) of produced rice, and Figures 3 (a) to ('3) are FIG. 4 is a sectional view showing a method of manufacturing an embodiment of P-channel J-F)LT according to an embodiment of the present invention, and FIG. FIG. In the figure, (1) tJin type semi-solid substrate, (2) ri
P-type epitaxial growth layer, (4) is P-type impurity layer (source region), (5) is P-type high impurity drain head, (
6) is the upper gate region, (9)/″i source voltage, I character,
(10) is the drain electrode, (11) is the gate electrode, (1
2) is n shadow region, (14) is silicon r dredging 1 return, (1
5) P8 G rg, (18) is a silicon oxide film eaves.The same reference numerals in the figures are the same (Shin Kuzuno, the agent who indicates the target part). Figure 4

Claims (1)

[Claims] The first step is to form a silicon oxide film of porridge 1 on the surface of the 4 halves and the 4 plates, and the second step is to selectively remove the silicon oxide 1 odor of na-1trJ1 and expose a part of the surface. Process and silicon oxidation of 1JIJ6selffJ1! A third step of doping impurities on the surface of the hollyhock to form an iL layer, a fourth step of forming a silicon oxide layer of fJ2 on the protective film, and a selective step of doping in the second step. a fifth step of exposing a part of the exposed surface again without removing the protective film; and forming electrolytic wax on the surface of the substrate that has been carved into a shape in the fifth step. a sixth step of manufacturing a semiconductor device.