JPS59112350A - Program monitoring control method - Google Patents

Abstract

PURPOSE:To obtain an efficient debugging system only by adding a small number of hardwares by using a bit with optional address width or a bit with optional data width for comparison. CONSTITUTION:A command from a console 25 is analysed by an analysing part 24 and supplied to a compare data setting part 22 and a selecting circuit 20. A setected signal from the selecting circuit 20 is supplied to a bit extracting circuit 26. The bit extracting circuits 26, 27 extract effective bits respectively on the basis of the contents of an effective bit position register 31. The outputs of the circuits 26, 27 are inputted to a comparison operation part 23 through registers 28, 29, respectively. The operation part 23 compares the contents of the register 28 with that of the register 29, and at the time of coincidence, a stop signal is outputted to a CPU1 through a control signal line 12 to stop the CPU1.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a program monitoring control system, particularly a program monitoring mechanism for facilitating program debugging. The present invention relates to a program monitoring control system that allows control such as matching stop to be performed by paying attention to only arbitrary bits of an address or data width.

(13) Prior Art and Problems FIG. 1 shows an example of the conventional method. The central processing unit 1 is a device that sequentially fetches and executes instructions stored in a memory 2. The address of the instruction is supplied to the memory 2 via the address bus 6, and the instruction data is read to the central processing unit 1 via the data bus 7. This exchange of address signals and data signals is performed based on control signals on the control signal line 8. The service processor 3 is a subsystem having one processor independent of the central processing unit 1, and has various system control functions and operation control functions. One of them is an address/data compare control function 9, which allows the central processing unit 1 to be stopped when a certain address in the memory 2 is accessed, for example.

This address/data conveyor control is performed by a comparison designation unit 5 and a comparison unit 4, and the comparison designation unit 5 designates a fetch address, a store address, etc. to be stopped. This designation information is transmitted to the comparison address data line 9. The signal is transmitted to the comparison section 4 via the comparison data line 10 or the control signal line 11, and the comparison section 4 performs control when the content of the signal on the address bus 6 or data bus 7 matches the content specified by the comparison specification section 5. A stop signal is output to the central processing unit 1 via the signal line 12.

According to the above-mentioned conventional method, the comparison specification section 5 had to specify all bits of the address or data width.

Therefore, there is a drawback that, for example, when debugging software, it is necessary to change the address to ensure that the instruction address can be grasped before execution. This problem can be solved by having multiple comparison circuits in hardware.

The amount of hardware will increase significantly.

(q Purpose and Structure of the Invention The present invention aims to solve the above-mentioned problems and to provide an efficient debugging system with the addition of a small amount of hardware.Therefore, the present invention By comparing the bits or arbitrary bits of the data width, it is possible to specify a range of addresses and displacement from the base address. This is to enable comparison.In other words, 2
The four-gram monitoring and control method of the present invention includes a comparison data setting unit that sets comparison data for an arbitrary bit of an address or data width consisting of a plurality of bits in a data processing device that includes at least a central processing unit and a storage device. , a comparison data extraction unit that extracts valid bits corresponding to the comparison data from the address signal or data signal between the central processing unit and the storage device; The present invention is characterized in that it is equipped with a comparison calculation unit that performs a comparison calculation between the address signal and the data extracted from the address signal or data signal, and program monitoring control is performed based on matching arbitrary bits of the address or data width. Embodiments will be described below with reference to the drawings.

Embodiment of the Invention FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of an embodiment of program monitoring commands, and FIGS. 4 and 5 are diagrams explanatory of a control mode according to an embodiment of the present invention. shows.

In the figure, 1.2.3.6.7.8.12 corresponds to FIG. 1, and 18 is a real address/logical address switching circuit.

19 is an address conversion section, 20 is a selection circuit, 21 is a comparison data extraction section, 22 is a comparison data setting section, 23 is a comparison operation section, 24 is a command analysis section, 25 is a console, 26 and 27 are bit extraction circuits, 28 and 29 are registers, 30 is a comparison data register, and 31 is a valid bit position register.

Instructions for monitoring programs executed by the central processing unit 1 are given by commands from an operator console 25 connected to the service processor 3. Figure 3 shows an example of this command.

The command C1 shown in FIG.
This command instructs that the central processing unit 1 should be brought to a halt state when instructions or data in the range of address 23FFJ are fetched. Command C2 is a command that instructs to stop when the last three digits of the real address are l'-456J. That is, in this case, address "000456", address "001456 J, l
-002456J address, ... "The central processing unit 1 will be stopped when any of the instructions etc. at the discrete real addresses of the FFF456J address are fetched. Command C3 is the command C1 fetches the instruction/data etc. This command instructs to stop the process when the data is written into the memory 2, whereas it instructs the process to stop when the data is written to the memory 2.

The target address range is the same as command C1.

The same applies to command C4.

Commands C5 to C8 are for the case where the comparison target is not an address but the contents of data. It is assumed that the data is 16 bits. Command C
5, the data written to memory 2 is roOAOJ, [
oIAO'J, l-02AOJ, ... "FFAOJ
In either case, an instruction is given to stop the central processing unit 1. Command C6 is.

Instructs to compare when reading data from memory 2. Command C7 is similar to command C5, but further limits the addresses to which data is written. That is, 2.For example, if data "89AOJ" is written to the logical address r012366J, the central processing unit 1 is stopped.The command C8 is 2, for example, the real address r12.
When data "OBC7J" is read from address 0456J, the central processing unit 1 is stopped.

When the above command is input from the console 25, the command analysis section 24 analyzes the command.

Then, according to the analysis result, the comparison data register 30 and the valid bit position register 3 of the comparison data setting section 22 are
1, information regarding command parameters is set.

The comparison data set in the comparison data register 30 is address data or data handled by a program. The information set in the valid bit position register 31 is as follows.

For example, the bit of the part corresponding to the effective value of the parameter of the command shown in Figure 3 is set to "1", and "
As indicated by "x", the part that can take any value is determined to be "o".

Further, the command analysis section 24 outputs a selection signal to the selection circuit 20 depending on the contents of the command. The selection circuit 20 selects a real address signal, a logical address signal, or a data bus 7 from the address bus 6 according to the content of the selection signal.
This is a circuit that selects a data signal from. The timing of taking in a signal and whether the data signal is read data or write data are determined based on the control signal on the control signal line 80. Note that the address signal from the central processing unit 1 is switched by the real address/logical address switching circuit 18 to pass through the address converter 19 or not, and when the address signal indicates a logical address, the address signal is The conversion unit 19 performs address conversion from a logical address to a real address.

The signal selected by the selection circuit 20 is supplied to a comparison extraction circuit 27. Bit extraction circuits 26 and 27
In each step, valid bits are extracted based on the contents of the valid bit position register 31. For example, the bit extraction circuits 26 and 27 are constituted by AND circuits, and for bit values that can be any value, both the data selected by the selection circuit 20 and the comparison data from the comparison data register 30 are set to "0". It can be considered that only the numerical part that is valid for comparison is left out. Of course, by OR circuit etc.
Both bit parts to be ignored may be set to "1".

The outputs of the bit extraction circuits 26 and 27 are input to the comparison calculation unit 23 via registers 28 and 29, respectively.

The comparison calculation unit 23 compares the contents of the register 28 and the register 29.
If they match, a stop signal is also output to the central processing unit 1 via the control signal line 12 to stop the central processing unit 1. In addition, the command C7 shown in FIG.
When the content of data in a specific address range such as C8 is the issue, for example, 7 addresses are first compared, and when the address matches, the data content is then compared. Also, the comparison data extraction unit 21. Two sets of comparison calculation units 23 and the like may be prepared, one for addresses and one for data from the data bus 7.

The bit extraction circuits 26 and 27, the comparison calculation unit 23, etc. can be constructed by simple logic circuits, but they may also be realized by a microprogram control mechanism included in the service processor 3.

FIG. 4 and FIG. 5 are explanatory diagrams for explaining two examples of control using the present invention. For purposes of explanation, it is assumed that the address is represented by 8 bits.

In the case shown in Figure 4, "
x2" address is specified. in this case.

As shown in FIG. 4, a comparison data register 30 is provided.

"XXXX0010" is set in binary. The 4 bits represented by "x" may be "0" or "1". The effective bit position register 31 contains 2, for example r in binary.
The value of oooollllJ is set.

This value results in the "0" portion being excluded from comparison. Therefore, when the address in the shaded area of the memory 2 shown in FIG. 4 is accessed, a stop signal to the central processing unit is output.

In other words, in this example, the relative position from a certain boundary is valid.

For example, it is very useful when performing program monitoring regarding a specific relative address of a segment or page that is a processing unit of software.

FIG. 5 shows an example of control regarding tracing. Program monitoring is not limited to simply stopping the central processing unit, but also involves address tracing. In FIG. 5, reference numeral 32 represents a trace buffer. In tracing, when an instruction in a specified address range is fetched, the address information is accumulated in a trace buffer 32 prepared in advance.2 For example, when an abnormality occurs and the central processing unit stops, the By dumping the contents of trace buffer 32.

This is done so that the cause of the abnormality can be investigated.

When the trace buffer 32 becomes full.

The latest address information overrides the oldest address information. Specific examples of trace-related commands will not be explained here, but 2For example, when "5x" is specified as the trace address range, the comparison data register 3 (1: is a binary number as shown in Figure 5). "010
1××××” is set.

The valid bit position register 31 contains l'-1111
0000J is set. Therefore, when an instruction between address l'-50J and address "5F" is fetched to the central processing unit by the output signal of the comparison operation section,
The address information is sequentially stored in the trace buffer 32.

Further, the comparison calculation section, bit extraction circuit, etc. may be realized by a microprocessor instead of a wire logic.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention provides flexible and efficient program monitoring with the addition of only a small amount of software, particularly those related to operating systems. Extremely useful for debugging programs. Easy to operate.

[Brief explanation of drawings]

Figure 1 shows an example of a conventional program monitoring control system. FIG. 2 shows the configuration of an embodiment of the present invention, FIG. 3 is an explanatory diagram of an embodiment of program monitoring commands, and FIGS. 4 and 5 are diagrams illustrating a control mode according to the embodiment of the present invention. In the figure, 1 is a central processing unit, 2 is a memory, 3 is a service processor, 21 is a comparison data extraction section, 22 is a comparison data setting section, and 23 is a comparison calculation section. Patent applicant Fujitsu Limited

Claims (1)

[Scope of Claims] A data processing device including at least a central processing unit and a storage device, comprising: a comparison data setting unit that sets comparison data for an arbitrary bit of an address or data width consisting of a plurality of bits; and a comparison data extraction unit that extracts valid bits corresponding to the comparison data from the address signal or data signal between the storage devices. a comparison operation section that performs a comparison operation between the comparison data and the data extracted from the address signal or data signal based on the result extracted by the comparison data extraction section, and based on matching of arbitrary bits of the address or data width. A program monitoring control method characterized by performing program monitoring control.