JPS59109942A - Programmable controller - Google Patents

Abstract

PURPOSE:To reduce a load for transmission processing, and also to reduce a load for preparing software by detecting automatically the head of a transmission text, when transmitting information to an from a program loader, and comparing it witn an STX code. CONSTITUTION:When a reception interrupting signal 6A is inputted to a controlling circuit 1-1 through an interruption detecting circuit 1-2 from a transmitting device 6, the received data is read out by one type from the transmitting device 6, in a received data readout circuit 1-3 by its control signal, and said data is compared with an STX code by a text head detecting circuit 1-4. When they coincide with each other, a coincidence signal 14A is sent to the controlling circuit 1-1, an STX detection request flag is reset, an operation of a data storing gate is permitted, and a receiving text is written in a received data store memory 5-4.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a programmable controller and detects the beginning of a transmitted text, decodes and sets data length in a microprogram in information transmission between a program loader that performs online monitoring, The present invention relates to a microprogram-controlled programmable controller that reduces the load on control software and reduces recovery processing when a transmission error occurs.

[Technical background and problems]

During programming, a programmable controller (hereinafter abbreviated as PC) receives programming information from a program loader (hereinafter abbreviated as PL) and stores it in a memory. Also, during online monitoring, necessary data is transmitted to the PL in accordance with a request indicated by a command in the transmission text from the PL.

If the PC has a transmission device for exchanging various information with the PL and performs that service, KVi accepts transmission/reception interrupts from the transmission device, and the PC's CP responds accordingly.
A common method is to send and receive data between the U and the transmission device.

In this method, each time a byte of data is received, the CPU must read it from the transmission device and determine whether it is normal data and which part of the transmitted text it corresponds to). Ivy. Especially when a special transmission format is used, such as when transmitting data between PL and PC, it is necessary to constantly compare the received data with a specific control code in order to detect text breaks. . The complexity of this interrupt processing is
This created a processing load, hindering speed-up of processing, and also created a burden on software creation.

In addition, if a transmission error occurs, P
Normally, C requests the PL to resend the transmitted text, but in conventional processing, an interrupt is generated every time, although the last data salt of the text can be ignored from the data where the transmission error occurred. Complicated processing was performed each time it occurred. This leads to an increase in transmission processing and is also a cause of lowering processing efficiency.

The execution status monitoring function still requires high speed, so the CP
The load on U's interrupt processing is quite large. In addition, there was a drawback that adding other hardware to process this would result in high costs.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and it checks the received data using a microprogram, automatically detects the beginning of the transmitted text, and reduces the load on the transmission processing of the CPU of C. The purpose of this invention is to speed up other processing and reduce the burden of creating software for transmission interrupt processing.

[Summary of the invention]

The present invention provides an interrupt signal for each 1-byte received signal of a transmission text received by the transmission device in a programmable controller having a transmission device and transmitting and receiving information with a program loader by serial transmission. an interrupt detection circuit that generates an interrupt signal, a first memory circuit that stores a microprogram that starts operating in response to the interrupt signal, and a second memory circuit that stores control information of the transmission text. text length decoding means for detecting a text length (N) signal indicating the data length of the transmitted text; the second control information.
This is a programmable controller in which the control information setting means to be set in the memory circuit of the controller is performed by the microprogram to achieve high-speed processing and eliminate the need for a reception processing program based on ordinary instructions.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the configuration of a programmable controller according to the present invention.

The CPU 'x performs transmission with the program loader 8 via the transmission device 6 and the interface 7. The received data is stored in memory 5. 3 is a diagram showing the format of a transmission text for exchanging information between various processing devices 8. In FIG.

The transmission test consists of continuous byte data (8-bit data), and is roughly divided into two parts: a header part 1o and a data part 1o. The header part 10 is a start of text (hereafter (i S T
X To '1-) li TeTo'! ,'J,NextI'c.

This is followed by a command [2] indicating which various operations are requested of the PL. Next, the text length Ni indicating the length of the data part
3, followed by the complement of the text length N]4. The data portion 20 is composed of data 21 and a block check character (hereinafter abbreviated as BCC) 22 for checking the last data salt in sTX.

Further, various types of information related to transmission are stored in the memory 5 as an information table as shown in FIG. Information chiful is
It consists of an S'l'X detection request flag, a start address and an end address that respectively indicate the beginning and end of the data buffer, and an STX code storage area that stores the STX code.

Every time the transmission device 6 receives one byte of data from the program loader 8, it outputs an interrupt signal (hardware interrupt signal) to notify the CPU that it is ready for reading. When the CPU 1 accepts this interrupt signal, it temporarily suspends the processing currently being performed and transfers control to a special microprogram routine that performs reception processing. Therefore, this programmable controller can automatically perform special processing each time it receives or receives 1 byte of data from the program loader.

When attempting to start receiving data, the CPUI sets an STX detection request flag in the information table. This flag is a flag that instructs to find the beginning of the next transmitted text and store that transmitted text in the data storage area of the memory 5.

FIG. 4 is a functional block diagram representing the operation of actual reception processing.

The operation will be explained below using FIG. 4.

First, when the reception interrupt signal 6A from the transmission device 6 is input to the interrupt detection circuit Wr1-2, the interrupt detection circuit 1-2 detects that an interrupt has occurred and sends an interrupt detection signal to the control device 1-1. input. As a result, the control device 1-1 permits the operation of the received data reading circuit 1-3. Further, when the s'rx detection request flag (not shown) is set, the operation of the text head detection circuit 1-4 is also permitted.

The received data reading circuit 1-3 reads 5 bytes of received data from the transmission device 6, sends it to the text start detection circuit 1-4, and stores it in the S'l"X code holding memory 5-2. A comparison is made with the STX code. If the comparison result does not match, the reception process ends. If the comparison result matches, the text start detection circuit 1-4 sends a match signal 14 to the control circuit 1-1. Send A.

When the control circuit]-1 receives the match signal 14A, it resets the STX detection request flag (not shown) and permits the operation of the data storage gate 1-6. As a result, the operation of the text start detection circuit 1-4 is prohibited, and the data sent from the received data reading circuit 1-3 is transferred to the data storage game 1-1.
-6 to the received data storage memory 5-4.

The control circuit 1-1 increments the count value of the data counter 5-1 by 1 each time the received data is written into the received data storage memory 5-4 via the data storage gate l-6, and after receiving 8TX, the received text is are successively stored in the received data storage memory 5-4 one byte at a time.

Text length decoding circuit 1-intelligence data reading circuit 1-3
The text length N13 is read from the header part of the transmission text sent from the sender, checked with the number of text long sleeves N14, and stored in the control information memory 5-3.

The count value of the data counter 5-1 is the control information memory 5
When the count value determined by the text length N 1.3 stored in -3 is reached, the control device 1-1 starts a reception completion process. That is, the STX detection request flag (not shown) is set again to prepare for reception of the next transmission text, and the processing for initializing the data counter 5-1 is activated by a normal command.

When a reception error occurs, the control device 1-1 sets the STX detection request flag, and the rest of the currently sent text can be read and discarded by simply passing through the text start detection circuit 1-4. Processing when an error occurs can be minimized.

FIG. 5 is a flow chart of the above reception process.

〔Effect of the invention〕

As mentioned above, according to the programmable controller of the present invention, not only does the program using normal instructions for STX detection necessary when receiving the above-mentioned transmission text become unnecessary, but also the processing using a microprogram In addition, processing using normal commands is performed only when reception is completed, so there is little impact on normal processing, and the interrupt processing program is also easy, greatly reducing the burden of software creation. Also, when a transmission error occurs, the STX detection request flag is set,
The subsequent unnecessary data can be skipped at high speed through microprogram processing, resulting in high processing efficiency b0

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the programmable controller of the present invention, FIG. 2 is a configuration diagram showing the format of transmission text, FIG. 3 is a diagram showing an example of an information table that stores control information, and FIG. FIG. 5 is a functional block diagram for explaining the processing functions of the microprogram of the present invention, and is a flowchart thereof. l...CPUl-1...Control circuit 1-2...Interrupt detection circuit 1-3...Received data reading circuit 1-4...Text start detection circuit 1-5...Text length decoding Circuit 1-6...Data storage gate 2...Microprogram bus 3...Microprogram memory 4...CPU path 5...Memory 5-1...
- Booter rank 5-2... STX code holding memory 5-3... Control information memory 5-4... Received data storage memory 6... Transmission device 7... Interface 8.
・Program loader

Claims (1)

[Claims] In a programmable controller that has a transmission device and sends and receives information to and from a program loader by serial transmission, an interrupt signal is generated for each 1-byte reception signal from the transmission text reception signal received by the transmission device. An interrupt detection circuit, a first memory circuit that stores a microprogram that starts operating in response to the interrupt signal, and a second memory circuit that stores control information for the transmission text are provided, and a start signal indicating the beginning of the transmission text is provided. a text head detecting means for detecting an obtext I-(STX) signal; and a text length (
N) A programmable controller characterized in that the text length decoding means for detecting the signal and the control information setting means for setting the text length (N) signal as the control information in the second memory circuit are performed by the microprogram. .