JPS59104879A - Solid-state image sensor and camera - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a solid-state imaging device for obtaining a video signal using only a single plate or two plates.

(Prior art) Conventional single-chip or two-chip solid-state imaging devices can handle each color by inputting light into a light receiving section through an optical means for color separation, such as a striped or mosaic color filter. Electrical information is formed in each pixel, and the electrical information of each pixel is read out in time series via a common transfer path.

FIG. 1 shows an example of a solid-state imaging device used in a conventional solid-state imaging device, which is a frame transfer type (F T ) iQ CCD (ChMRge). This is a part for storing charge information of each pixel in the light receiving section. 3 is a horizontal shift register as a transfer path, which takes in information from a part of the memory one horizontal line at a time, and then transfers this line information horizontally. By transferring in the direction, a point-sequential signal is obtained.

Therefore, for example, a striped filter as shown in Fig. 2 is installed in front of the light receiving part, and R (red), G (green), B (blue) are
By matching the pitch of each color filter to the pixel pitch of the light receiving section, each pixel forms a signal corresponding to each color, and the horizontal shift register 6 obtains point-sequential color signals.

Each color signal thus obtained is converted into, for example, an NTSC signal by a signal processing circuit as shown in FIG.

That is, the point sequential imaging output signal output from the CCD amplifier 4 is first separated into three sample and hold circuit signals EB. Further, the levels of the color signals PR, Eo, and Ea are adjusted in variable gain amplifiers 9 to 11, respectively, and the white balance is controlled.

The level-adjusted color signals are sent to process circuits 12 to 12 including a clamp circuit, a γ correction circuit, an aperture correction circuit, etc.
After being processed at 141C, the matrix circuit 15 converts the luminance signal and color difference signal 11F'', and encodes the signal into an NTSC signal by the encoder 16.

With this force configuration, first the horizontal shift register 3 is 3
Since it focuses on reading out the primary colors sequentially, in order to read each on a 3.58H2 carrier, 3.58x 5-1Q
, 74 MHz clock.

However, lowering the clock frequency lowers the transfer efficiency and requires more power, which is an obstacle to increasing the number of pixels in the horizontal shift register, that is, the number of pixels in the horizontal direction of the imaging unit 1. .

(Objective) It is an object of the present invention to provide an improved imaging device that can eliminate the drawbacks of the conventional solid-state imaging device.

Another object of the present invention is to provide an image sensor that does not require a sample circuit for signal separation.

Another object of the present invention is to provide an image pickup device that has less noise, can drive horizontal registers at low speed, and thus has good transfer efficiency, and an image pickup device using this image pickup device.

(Example) The present invention will be described in detail below based on Examples.

FIG. 4 is a diagram showing an example of the configuration of an imaging element used in the imaging device of the present invention, in which a filter as shown in FIG. 2 is pasted on the surface of the imaging section. 31-33 are horizontal shift registers, and 41-43 are charge-voltage conversion amplifiers, respectively.

As described above, in this embodiment, three horizontal shift registers are provided as transfer paths for reading, and charges corresponding to each color are separated and temporarily stored in the respective horizontal shift registers.

Therefore, each color signal is substantially sampled in each register, and each color signal is separated and outputted from the amplifiers 41 to 43, respectively.

Next, FIG. 5 is an electrode configuration diagram of a main part of the image pickup device shown in FIG.

Although not shown in FIG. 4, a charge clear drain CD is provided adjacent to the bottom end of the image sensor of this embodiment, that is, below the horizontal shift register 31.
The power level is connected.

Further, between the memory part 2 and the three horizontal shift registers, there is provided information for three colors included in the horizontal line of the memory part 2 to be separated and stored in the three horizontal shift registers 31 to 36 in sequence. A separating section 17 is provided.

In the figure, the shaded area is the channel stop, 61E~ in the figure.
33g is each transfer electrode of the horizontal shift registers 31 to 33, 17E is a transfer electrode of the separation section, and 2E is a transfer electrode of a part of the memory.

In this example, data is transferred using a one-phase drive method, but it may be a two-phase, three-phase, or even four-phase drive method.

In the figure, the parts labeled A, B, C, and D constitute one cell, and if the potentials of each part of j5, A, and D are expressed as P(A) to P0, then P 9 virtual electrodes (Virtual electrodes) such as ion implantation etc.
alPhase) is formed and the potential level is fixed. Also, the potential of the parts C and D under each transmission electrode is always set so that P (C) > P (θ, and when a high level potential is applied to each electrode, P (A) >P@>P(C)>P(DJ, and when a low level potential is applied, P(C)>P(Di>
It is configured such that P(A)>P(B).

Note that φ1 to φ- are the clocks applied to the electrodes 31E to 33g, φd is the clock applied to the electrode 17E, φS is the clock applied to the electrode 2E, and φCL is the clock applied to the clear gate C1. be.

FIGS. 6(a) and 6(b) are diagrams showing the clock timing of vertical transfer and the timing of horizontal transfer, respectively.

Further, FIG.
, 6 (a), (b) as shown in 01/φ1. ψS
.

ψding, ψl~ψ8. Supply ψCL. 19 is a reference signal generator. As is clear from the figure, in this configuration, a sample and hold circuit for sampling and holding each color information is omitted, resulting in a simple configuration.

To explain the operation of this configuration, during vertical transfer, the period tl-1 is synchronized with the vertical synchronization signal as shown in FIG. 6(a).
ψ1 during s. ψS, ψT, ψ8. ψS, ψl.

As φCL, pulses synchronized with each other and having substantially the same phase are supplied and stored at least as many times as the number of baking soda pixels of the imaging section. After that, after time ts, the charge information of a part of the mesori is shifted by 12 inches by the pulse ψS, and the pulse nails ψB, ψS, and ψl are driven as shown in the figure, so that the information of 3 pixels in the horizontal direction is transferred into 3 lines. shift registers 31 to 3
The information in each register is sequentially read out after time t4.

FIG. 6(b) shows this line-by-line vertical shift and read operation. At the first rising edge of pulse ψT, for example, 116.
The charges in 117 and 118 are 111 and 11, respectively.
4. Enter 115. Thereafter, the pulses φ and φ-9φl are sequentially supplied, so that the charge at the 1150 portion moves to 100 and is accumulated there.

Also, during this time, the charges at parts 114 and 111 are 113, respectively.
, move to 110.

Also, when the second pulse φT is supplied, 113, 11
The charge of 0 is transferred to 112 and 109, respectively, and this pulse ψ
The charges of 112 are moved to 10 by the pulses φl and ψ which immediately follow T, and then transferred to 102 and accumulated by the fall of the pulse ψ. Also, during this period, the charge at 110 moves to 105 and is accumulated at 104 after the fall of pulse ψ3.

As a result, the charges in the bottom row of a part of the memory are distributed and accumulated in each shift register pixel by pixel via the separating section 17. Therefore, for example, if the R, G, H stripe filter is 1) L, l[ is G, II
When pasted so that I corresponds to B, V raster 31VCJ
r! ,,R+, charges corresponding to G are accumulated in the register 62 and charges corresponding to B are accumulated in the v dimeta 33.

Thereafter, after time t4, the charges in each register are sequentially read out. By repeating such operations, all horizontal lines in a part of the memory can be read out.

The configuration above is a frame transfer type CCDK.
As mentioned above, the interline type CCD9C
P n (Charge Priming Device
It goes without saying that it can be applied to all (e) in the same way.

Further, the shift register of the present invention is capable of separately accumulating charges for each color separated by an optical system for color separation such as a color separation filter, and the color separation filter may be a combination of complementary color filters or the like. It goes without saying that you may also use .

Moreover, instead of a striped filter, a zaic-like filter may be used.

Furthermore, the clock cycle of the registers can be halved by simply using two horizontal registers instead of three and separating the color signals and storing them in each register. Of course, if the color separation optical system uses three or more colors, the number of registers may be three or more accordingly.

Furthermore, although a clear drain and a clear gate are provided in this embodiment to clear unnecessary charges, it is possible to separate and simultaneously perform color information according to the present invention even without these. (Effect) According to the present invention, each color signal Since there is no need for a sample and hold circuit for synchronization, the configuration is simplified.

Furthermore, since the transfer lock frequency of each horizontal register can be greatly reduced, transfer efficiency can be maintained even if the number of pixels in the horizontal direction is increased, and there are many effects such as no noise.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of a conventional frame transfer type COD, Fig. 2 is a diagram showing an example of a stripe filter, Fig. 3 is a diagram showing the configuration of a conventional signal processing circuit, and Fig. 4 is an image pickup device of the present invention. FIG. 5 is a diagram showing a main part configuration of the device shown in FIG. 4, and FIG. 6(a) is a diagram showing an embodiment of an image pickup device suitable for. (b) is a vertical transfer timing diagram and a horizontal transfer timing diagram of the device, respectively, and FIG. 7 is a diagram showing an example of the configuration of an imaging device using the device. 1... Imaging unit, 2... Part of memory, 31 to 33...
・Horizontal shift register, 41-43@...amplifier. 444-4 4141 Procedural Amendment (Voluntary) Commissioner of the Patent Office Kazuo Wakasugi 1. Indication of the case.”
; :/-'-2't 9 '/' / /Showa 57
Patent application filed on December 71, 2015 (11) 2, name of the invention solid-state image sensor 3, relationship with the person making the amendment case Patent applicant address 3-30-2 Shimomaruko, Ota-ku, Tokyo Name <100
)Representative of Canon Co., Ltd. Ryu Kaku Part 4, Agent residence 3-30-25 Shimomaruko, Ota-ku, Tokyo 148, ffR16 of [Increase due to amendment], Subject of amendment (1) Specification (2) Figure 6 (a) and (b) of the drawings 7. Contents of amendment (1) The entire statement of the specification is amended as stated in the attached amended specification. (2) Replace Figures 6(a) and (b) of the drawings with Attachment 11f4. 8. List of attached documents (1) Corrected description 1 copy (2) Corrected drawings Figures 6 (a) and (b) (replacement) 1 copy (corrected) description 1. Name of invention Solid-state image sensor 2 Detailed Description of the Invention (Technical Field) The present invention relates to a solid-state imaging device, particularly a solid-state imaging device suitable for obtaining color imaging signals. (Prior Art) Conventionally, when obtaining a color imaging signal with color signals of three or more colors using one or two solid-state imaging devices, an optical system for color separation such as a striped or mosaic color filter has been used. By receiving light into the imaging section of the image sensor through the member, electrical information corresponding to each color is formed in each pixel,
The electrical information of each pixel is read out in time series through a common transfer path. Figure 1 shows an example of a conventionally known solid-state image sensor, which is a frame transfer type (FT).
CCD (Charge Coupled Device)
This shows about e). Reference numeral 2 denotes an imaging section, which is composed of a plurality of pixels for photoelectric conversion arranged in rows and columns. Reference numeral 2 denotes a part of the memory, which is a part for storing charge information of each pixel of the imaging section l. Reference numeral 3 denotes a horizontal shift register as a transfer path for reading, which takes in information from the memory part 2 one horizontal line at a time and transfers this line information in the horizontal direction to obtain a dot-sequential signal. Therefore, for example, a striped color filter for color separation as shown in FIG.
, G (green), and B (blue) by matching the pitch of each pixel of the image pickup section I, the pixels of each column form a signal corresponding to each color, so the horizontal shift register 3 A point-sequential color signal is obtained from the . Each color signal obtained in this manner is converted into, for example, an NTSC signal by a signal processing system as shown in FIG. That is, the point-sequential imaging output signal outputted from the CCD amplifier 4 is first subjected to sample-holding of each color signal in a signal separation circuit 8 consisting of three sample-and-hold circuits 5 to 7, and is then converted into a red signal ER, a green signal EC, and a green signal EC. Blue signal EB
separated into The levels of the color signals ER, EG, and EB are adjusted in variable gain amplifiers 9 to 11, respectively, and the white balance is controlled. Each level-adjusted color signal is processed in process circuits 12 to 14 including a clamp circuit, a γ correction circuit, an aperture correction circuit, etc., and then converted into a luminance signal and a color difference signal in a 7-trix circuit 15, and then sent to an encoder. 16, the signal is converted into, for example, an NTSC signal. With this configuration, the water 11 shift register 3 becomes 1t for sequentially reading out the three primary colors, so each of the three primary colors is 3.58 t.
3.58MH for reading on a MHz carrier
It must be driven with a clock of 2X 3 = 10.74 Mn2, but increasing the clock frequency will lower the transfer efficiency and increase power consumption, so the number of pixels in the horizontal shift register, That is, this has become an obstacle when increasing the number of pixels in the horizontal direction of the imaging section l. (Objective) It is an object of the present invention to provide a solid-state image sensor suitable for improved color imaging that can overcome the drawbacks of the conventional solid-state image sensor. Another object of the present invention is to provide a solid-state imaging device in which, for example, a sample-and-hold circuit for color signal separation is unnecessary or can be extremely simplified. Another object of the present invention is to provide a solid-state image pickup device that has less noise, can drive horizontal registers at low speed, and has good transfer efficiency. (Examples) The present invention will be described in detail below based on Examples. FIG. 4 is a diagram showing an example of the configuration of a solid-state imaging device according to the present invention, in which a color stripe filter for color separation as shown in FIG. 2 is attached to the front surface of the imaging section. 31-33 are horizontal shift registers, and 41-43 are charge-voltage conversion amplifiers, respectively. In this way, in this embodiment, the water shift register as a read-out transfer path is obtained depending on the type of color signal.
Books (31 to 33) are provided, and charges corresponding to each color are distributed and input into dedicated horizontal shift registers 31, 32, and 33, respectively, and are read out. Therefore, each color signal is transmitted to each horizontal register 31°32.33
sampled substantially at the amplifier 41.42.43
, each color signal is separated and output. Next, FIG. 5 shows the electrode configuration of the main part of the image sensor shown in FIG. ing. Although not shown in FIG. 4, a charge clear drain CD is provided through a charge clear gate CL adjacent to the bottom end of the image sensor of this embodiment, that is, below the horizontal shift register 31, and the drain A power level is connected to the CD. In addition, the memory part 2 and the three water shift registers 31 to 3
3, three horizontal shift registers 31 to 3 are used to store the information of the three colors included in the last horizontal line of the memory part 2.
A separate input section 17 is provided which performs parallel-to-serial conversion of charges in order to distribute and input them to each of 33. In the figure, the shaded areas are channel stops, 31E to 33
E denotes each transfer electrode of the horizontal shift registers 31 to 33, respectively;
17E is a transfer electrode of the separation input section 17, and 2E is a transfer electrode of the memory part 2. In the non-embodiment, the configuration is such that the transfer is performed by l-phase drive, but this may be two-phase, three-phase, or even four-phase. In the figure, one set of parts indicated by A, B, C, and D constitutes a unit cell, and the potential of each part from A to D is set to P (A
) ~ P (D), then p (A) >
A virtual electrode (V
virtual phase) is formed, and the potential level is fixed. Also, the parts C and D under each transmission electrode
The potential of is always set so that P (C) > P (D), and when a low level potential is applied to each electrode, P (A) > P CB) > P (C)
>P (D), and when a low level potential is applied, P (C) > P (D) > P (A) > P (
B). Incidentally, if expressed in terms of potential, the relationship is opposite to that in the case of potentials P (A) to P (D). Note that φ1 to φ3 are clock pulses applied to the electrodes 31E to 33E, φT is a clock pulse applied to the electrode 17E, φS is a clock pulse applied to the electrode 2E, and φ
CL is a clock pulse applied to the electrode of the clear gate cL. FIGS. 6(a) and 6(b) show the clock timing of vertical transfer and the timing of horizontal transfer, respectively. Further, FIG. 7 is a block diagram schematically showing a color imaging system using an embodiment of the imaging device according to the present invention described above.
18 is a driver as a control f stage, and is shown in FIG.
Clock pulses φ■, φS, as shown in a) and (b)
φT, φ1 to φ3. φCL is supplied. Note that φ■ is a clock pulse applied to the electrode of the imaging section 1. 19 is a reference signal generator. As is clear from the figure, in this configuration, a sample and hold circuit for separating each color information is omitted, resulting in a simple configuration. To explain the operation of the configuration shown in FIG. 5, as shown in FIG. 6(a), when charges are vertically transferred from the imaging section 1 to the memory section 2, the vertical synchronizing signal V is used. In synchronization with 5YNC, period 1. -12 clock pulses φ■, φS, φT, φ3, φ2, φ1. As φCL, clock pulses that are synchronized with each other and have approximately the same phase (however, as shown in the figure, only the clock pulse φS slightly precedes the other clock pulses) are set at least as many times as the number of vertical pixels of the imaging unit l. By supplying the same amount, the charge remaining in the memory part 2 is discarded to the drain CD. The charges in the imaging section 1 are transferred to the memory section 2 and stored therein. Thereafter, after time t3, the accumulated charge information in the last row of memory part 2 is shifted by one line by clock pulse φS, and clock pulses φT, φ3, φ2, φ
1 as shown in the figure, information in the horizontal direction is inputted to each of the three horizontal shift registers 31 to 33, divided into three pixels, and furthermore, after time t4, the information in each register is read out sequentially. Here, in particular, the operation between times t3 and t4, that is, when the information of the last line of the memory part 2 is appropriately distributed and inputted to each of the three water shift registers 31 to 33 through the separation input section 17. Regarding the operation of Figures 5 and 6 (a
), (b) will be described in detail. For the sake of simplicity, in Figure 5, ■. We will only explain the movement of charge information in the three columns of the memory part 2 shown by ■ and ■, but it goes without saying that the same operation can also be performed in each column of the other sets (three columns and one set). Needless to say, they are both triggered at the same time. First, at time t3, when the clock pulse φd goes high, 118, 11?
, +18 move to the portions Ill and 114 and 115 in the separate input section 17, respectively, and then, when this clock pulse φ goes low,
The charges transferred to the parts Ill and 114.115 are further transferred to the parts shown by 110, 113, and 108, respectively.Then, clock pulses φ3, φ2, and φl are sequentially generated with a slight delay after the clock pulse φd. At this point, the charge in the section 108 of the separation input section 17, that is, the charge that was initially stored in the section 118 of the column indicated by 1 in the memory section 2, is transferred to the section 105 and +04 of the horizontal register 33. The clock pulse is transferred through the portion shown by , the portion shown by 103 and 102 of the horizontal register 32, and the portion shown by 101 of the horizontal register 31 to the portion shown by 100 of the water register 31, where it is accumulated. When φT is given, the charges in the Ill and 114 portions of the separation input section 17 become 1, respectively.
Move through the section indicated by 09.112 to the section indicated by 108.108. Then, slightly delayed from clock pulse φ3, clock pulse φ3. When φ2 is added in order, the charge in the part 106 of the separation input section 17, that is,
Initially, the charges accumulated in the 117th part of the column indicated by ■ in the memory part 2 became 105. It moves through toa and the section 103 to the section 102 of the horizontal register 32, where it is accumulated. Next, when the clock pulse φτ is applied again and again, the charge in the portion 108 of the separation input section 17 moves to the portion 108 through the portion 1+07. Then, when the clock pulse φ3 is applied with a slight delay to the clock pulse φT, the electric charge that was in the 106 part of the separation input section 17, that is, the 116 part of the column indicated by ■ in the memory part 2, The charges accumulated in the horizontal register 33 move through the section 105 to the section 104 of the horizontal register 33, and are accumulated there. As described above, the charges accumulated in the last line of the memory part 2 are transferred to the dedicated horizontal shift registers 31 to 31 for each group of columns T, [, +11 by passing through the separation input section 17. 33 and are respectively distributed and input. Therefore, for example, if R, G, and B stripe filters are pasted so that the group in column ■ corresponds to R, the group in column H corresponds to G, and the group in column ■ corresponds to B, horizontal register 31 has R1, horizontal register 32 has G, horizontal register 33 stores charges corresponding to B1. After that, after time t4, each horizontal register 31°32.3
The charges inputted to 3 are read out respectively (0UTI to 0UT3 in FIG. 6(b)). Therefore, through the horizontal registers 31 to 33, the memory part 2
When the readout of charges for one horizontal line is completed, the sixth
As shown in Figure (b), a clock pulse φS is applied to the memory part 2, and the accumulated charge in each horizontal line is 1.
By moving the line horizontally in the vertical direction, a new charge is taken into one line of the most snoring, and then, by performing the above-mentioned operation between time t3 and t4, this new charge for one line is accumulated. Charges are distributed and input to horizontal registers 31-33. By repeating the above operations, the accumulated charges in all lines of the memory part 2 can be read out separately for each color. In addition, when horizontally transferring input charges in the horizontal registers 31 to 33, each register 31, 32 is set in the horizontal charge transfer mode in order to prevent charges from being mixed between the registers 31, 32, and 33. It is possible to add means such as a control gate to isolate each .33 from the others. Alternatively, by slightly modifying the waveforms of the clock pulses φ1, φ2, and φ3 in the horizontal transfer mode, it is possible to mix the charges between the horizontal registers 31 to 33 without adding any means for such isosort. It is also possible to perform horizontal charge transfer while preventing this. For example, at time t4, by first setting the clock pulse φ3 high prior to the clock pulses φ2 and φ1, the charge taken in the portion 104 of the horizontal register 33 corresponds to C of the electrode 33EF on the left side. Move to the part where you want to
Next, clock pulse φ2 is set high while keeping clock pulse φ3 high! 3 similarly transfers the charges captured in the portion 102 of the horizontal register 32 to the portion corresponding to C of the electrode 32EF on the left thereof, and then clock pulse φ3. Similarly, by setting clock pulse φ1 high while keeping both φ2 high, horizontal register 3
The charge taken in the 100 part of 1 is transferred to the part corresponding to C of the electrode 31EF on the left side, and this time, conversely, the long pulse φ1 is made low first, prior to the clock pulses φ2 and φ3. Horizontal register 3 by east
By transferring the charge that was in the portion corresponding to C of the electrode 31EF of No. 1 to the portion corresponding to A on the left side, and then setting the clock pulse φ2 to low, the charge on the electrode 32 of the horizontal register 32 is transferred.
The charge that was in the part corresponding to C of EF is transferred to the left part, and then, by making the clock pulse φ3 low, the charge that was in the part corresponding to C of electrode 33EF of the horizontal register 33 is similarly transferred to the left part. Charge transfer from the part corresponding to A to the part corresponding to C is performed in the temporal order of horizontal register 33 → horizontal register 32 → horizontal register 31, and from the part corresponding to C to the part corresponding to C. Conversely, for charge movement to the portion corresponding to A, the horizontal register 31
→Horizontal register 32 →Horizontal register 33 is performed in the chronological order, thereby preventing the mixing of charges in the horizontal registers 31 to 33 without adding the above-mentioned means for isolation. Transfer can be performed well. Now, in the embodiment described above, the information for one horizontal line of the imaging section 1 is divided into three parts and each of the three horizontal registers 31 to 33 is divided and read out. , the number of bits constituting each of the horizontal registers 31 to 33 is approximately 1/3 of the number of pixels in the horizontal direction of the imaging unit l, and therefore the clock pulses φ1 to φ to be applied to each
3 frequency can be reduced to approximately 1/3, thereby making it possible to save power, reduce noise, and improve transfer efficiency. Although only frame transfer type COD has been described as an example, interline type CCD and CP
D (Charge Priming Device
), which can be applied in exactly the same way. In addition, the horizontal shift register is used to separately capture and read out charges for each color separated by an optical member for color separation such as a color separation filter, and a single color separation filter may be a combination of complementary color filters, etc. It goes without saying that you may also use . Furthermore, instead of a striped color filter, a mosaic color filter may be used. Further, the clock frequency of the clock pulse for the horizontal register can be halved by simply using two horizontal registers instead of three and separating the color signals and storing them in each horizontal register. Of course, there are 3 colors separated by the color separation optical member.
If there are more colors, the number of horizontal registers may be three or more depending on the number of colors. Further, in this embodiment, a clear drain CD and a clear gate CL are provided to clear unnecessary charges, but color information can be separated even without these. In addition, horizontal registers 31 to 3
The isolation entrance portion 17 for the third electrode may be formed of a gate electrode. (Effects) According to the solid-state imaging device of the present invention, a sample-and-hold circuit for separating each color signal is unnecessary or extremely simplified, so that the configuration of the signal processing system is simplified. In addition, since the readout clock frequency of each horizontal readout section can be significantly reduced, transfer efficiency can be maintained well even if the number of pixels in the horizontal direction in the imaging section is increased, and noise can be reduced as well. It has many effects such as power saving. 4. Brief explanation of the drawings Figure 1 is a diagram showing the configuration of a conventional frame transfer type CCD, Figure 2 is a diagram showing an example of a striped color filter, and Figure 3 is an example configuration of a conventional color imaging signal processing system. FIG. 4 is a diagram showing an embodiment of the solid-state imaging device according to the present invention, FIG. 5 is a configuration diagram of the main part of the device shown in FIG. 4, and FIGS. FIG. 7 is a diagram showing vertical transfer timing and horizontal transfer timing of the device, and FIG. 7 is a diagram showing an example of the configuration of a color imaging system using the device. 1-1--imaging section, 2-----part of memory, 17--
1 separate input section, 31-33--1 readout section (horizontal register), 41-43--1 output amplifier.

Claims (1)

[Claims] (1) An image sensor that converts an original image into electrical information, a color separation optical means that color separates the source of incidence on the sensor, a plurality of transfer paths for reading out information in the image sensor, and the image 5. A solid-state imaging device comprising: control means for controlling the reading of each color information formed within the sensor via the different transfer paths.