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JPS59103455U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS59103455U
JPS59103455U JP1982199638U JP19963882U JPS59103455U JP S59103455 U JPS59103455 U JP S59103455U JP 1982199638 U JP1982199638 U JP 1982199638U JP 19963882 U JP19963882 U JP 19963882U JP S59103455 U JPS59103455 U JP S59103455U
Authority
JP
Japan
Prior art keywords
power supply
semiconductor equipment
supply pad
integrated circuit
showing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982199638U
Other languages
Japanese (ja)
Other versions
JPH0124933Y2 (en
Inventor
光久 清水
酒井　敏昭
名和田　一正
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1982199638U priority Critical patent/JPS59103455U/en
Publication of JPS59103455U publication Critical patent/JPS59103455U/en
Application granted granted Critical
Publication of JPH0124933Y2 publication Critical patent/JPH0124933Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は大規模集積回路を収容した半導体装置の一例を
示す断面図、第２図の４９０図は半導チップに形成され
るマスクスライス方式のパターン例を示す図であリイは
平面図、口はイの斜線で示すパターン部拡大図、第３図
は本考案の半導体チップパターン構成の一実施例を示す
平面図、第４図は本考案の半導体チップをパッケージに
収容して各パッド間をワイヤボンデング接続する要部平
面図、第５図は本考案の一実施例である電源パッド部を
示す拡大図、第６図、第７図は電源パッド部におけるワ
イヤ接続を示すための図であり、第６図はＡ−Ａ’　、
第７図はＢ−Ｂ’部を示す断面図　　。 である。 図中１１・・・・・・半導体チップ、１２・・・・・・
信号パッド、１３．１５・・・・・・電源パッド、１４
・・・・・・パターン導体、１６・・・・・・セラミッ
ク基板、１７・・・・・・ワイヤ、１８・・・・・・パ
ッド（メタライス）、１９・・・・・・二酸化シリコン
膜、２０．２１・・・・・・アルミニウム膜、　　　′
２２．２３・・・・・・絶縁膜。FIG. 1 is a cross-sectional view showing an example of a semiconductor device containing a large-scale integrated circuit, FIG. The opening is an enlarged view of the pattern portion indicated by diagonal lines in A. FIG. 3 is a plan view showing an example of the semiconductor chip pattern configuration of the present invention. FIG. Fig. 5 is an enlarged view showing the power supply pad part which is an embodiment of the present invention, and Figs. 6 and 7 are diagrams showing the wire connection in the power supply pad part. , and FIG. 6 shows A-A',
FIG. 7 is a sectional view showing the section BB'. It is. In the figure 11... Semiconductor chip, 12...
Signal pad, 13.15...Power pad, 14
...Pattern conductor, 16...Ceramic substrate, 17...Wire, 18...Pad (metal rice), 19...Silicon dioxide film , 20.21...aluminum film, ′
22.23...Insulating film.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路チップの素子周辺部に形成された第１の
電源パッドと該第１の電源パッドに接続され、集積回路
に動作電圧を供給する電源線上に形成された第２の電源
パッドとを有することを特徴とする半導体装置。It has a first power supply pad formed around an element of a semiconductor integrated circuit chip, and a second power supply pad connected to the first power supply pad and formed on a power supply line that supplies an operating voltage to the integrated circuit. A semiconductor device characterized by:
JP1982199638U 1982-12-28 1982-12-28 semiconductor equipment Granted JPS59103455U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982199638U JPS59103455U (en) 1982-12-28 1982-12-28 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982199638U JPS59103455U (en) 1982-12-28 1982-12-28 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS59103455U true JPS59103455U (en) 1984-07-12
JPH0124933Y2 JPH0124933Y2 (en) 1989-07-27

Family

ID=30425164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982199638U Granted JPS59103455U (en) 1982-12-28 1982-12-28 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS59103455U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125085A (en) * 1974-06-26 1976-03-01 Ibm
JPS53140983A (en) * 1977-05-16 1978-12-08 Hitachi Ltd Semiconductor integrated circuit
JPS5694041U (en) * 1979-12-20 1981-07-25
JPS59100550A (en) * 1982-11-30 1984-06-09 Mitsubishi Electric Corp Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125085A (en) * 1974-06-26 1976-03-01 Ibm
JPS53140983A (en) * 1977-05-16 1978-12-08 Hitachi Ltd Semiconductor integrated circuit
JPS5694041U (en) * 1979-12-20 1981-07-25
JPS59100550A (en) * 1982-11-30 1984-06-09 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0124933Y2 (en) 1989-07-27

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