JPS59100615A - Waveform shaping circuit - Google Patents

Abstract

PURPOSE:To waveform-shape and to reproduce a binary logical signal more accurately by connecting two comparator circuits having the same constitution and plural resistors connected in series as specified. CONSTITUTION:An input signal of voltage VS is fed in common to inputs 7, 8 of the comparators 5, 6. Resistors R5, R6 and R7 are connected in the order between the input signal and a power supply having a prescribed voltage VCC higher than the voltage of the input signal in series and a resistor R8 is inserted further. Other inputs 9, 10 of the comparator circuits 5, 6 are connected in common to a connecting point 14 of the resistors R5, R6. The voltage VCC is impressed to an output 11 of the comparator circuit 5. An output 12 of the comparator circuit 6 is connected to a connecting point 15 of the resistors R6, R7. Thus, the binary logical signal is waveform-shaped and reproduced more accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping circuit whose discrimination level has hysteresis and which is suitably used for receiving binary logic signals.

A typical prior art is shown in FIG.

It has one comparator circuit, two input terminals 2 and 3, and when the input terminal 20 level is higher than the voltage of the other input terminal 3, a high level signal VO)l is derived from the output terminal 4, and the input terminal When the voltage at the input terminal 2 is lower than the voltage at the other input terminal 3, a low level VOL signal is derived. Two input terminals are connected to a connection point between resistors R1 and R2 connected between output terminal 4 and ground.

FIG. 2 is a waveform diagram illustrating the operation of the prior art shown in FIG. FIG. 2 (2) shows the waveform of the output terminal 4. In FIG.
The signal applied to is indicated by the reference VT. Output terminal 4
After the output voltage reaches -H high level VOH, the output terminal does not reach the 4-digit low level until the input signal applied to the input terminal 3 becomes equal to or higher than the upper discrimination level VUP. Further, once the output terminal 4 becomes a low level, the output terminal 4 does not become a high level until the voltage vS applied to the input terminal 3 reaches the lower discrimination level VLP. The discrimination levels VUP and VLP are expressed by the first equation and the second equation.

In this way, the discrimination levels VUP and VLP have, so to speak, hysteresis. Therefore, a noise margin ΔV (-VUP-VLP) is obtained, and the input signal applied to the input terminal 3 has no noise.

Even if overshoots and undershoots are included, the pulse width can be accurately reproduced.

In the prior art shown in FIG. 1, the discrimination levels VUP and VLPd are fixed, and an accurate waveform cannot necessarily be obtained when the amplitude level of the input signal applied to the input terminal 3 varies.

Another prior art solution to this problem is shown in FIG. A capacitor C is connected to the input terminal 2 of the comparator circuit 1.
is connected. This capacitor C shifts the time at which an input signal is applied to input terminal 2 via resistor R3 and the time at which that input signal is applied to another input terminal 3, thereby ensuring that the comparator circuit l operates accurately. enable what is done. In connection with input terminal 2, resistor R3
and another resistor R4 are connected.

FIG. 4 is a waveform diagram for explaining the operation of the prior art shown in FIG. 3. The output signal of the output terminal 4 is shown in FIG. 410, and FIG. 4(2) shows the binary logic signals VSI and VS2 inputted from the outside. VSI and VS2 are collectively indicated as vS. The lower discrimination level VTLP when the output terminal 4 is at a high level and the upper discrimination level VTUP when the output terminal 4 is at a low level are expressed by the third and fourth equations. . The same reference numerals are provided corresponding to the previously described embodiments.

The lower discrimination level VTLPFi is expressed by the third equation.

When the voltage vS of the input signal is at a low level, it can be considered to be substantially constant regardless of its amplitude level, and the noise margin is indicated by Δv3 in FIG. 4(3).

The upper discrimination level VTUP varies greatly depending on the amplitude level vS of the input signal depending on the resistors R3 and R4 as shown in the fourth equation, for example, the amplitude level V of the input signal
S1. Noise margin ΔVl, Δ depending on the size of VS2
v2 changes in size. Therefore, when the amplitude level of the input signal is small like VS2.

There is a possibility that the noise margin Δv2 becomes small and malfunction occurs.

An object of the present invention is to provide a circuit that can more accurately shape and reproduce the waveform of a binary logic signal.

FIG. 5 is an electrical circuit diagram of an embodiment of the present invention. The pair of comparison circuits 5 and 6 have one input terminal 7.8 and the other input terminal 9 and 10, respectively.

They also have output terminals 11 and 12, respectively. Comparison circuit 5
．． 6 have the same configuration.

FIG. 6 shows a specific configuration of the comparison circuit 5.

This comparison circuit 5 is of the so-called open collector type,
The emitter of the output transistor 13 is grounded, and the collector is connected to the output terminal 11. When the voltage at one input terminal 7 is higher than the voltage at the other input terminal 9, the transistor 13 becomes conductive and the output terminal 11 becomes at a low level. When the voltage at one input terminal 7 is less than the voltage at the other input terminal 9, the transistor 13 is cut off, and the output terminal 11 is cut off.
will be released. Another comparison circuit 6 is also of the open collector type.

An input signal having a voltage ■S is commonly applied to one input terminal 7.8 of the comparator circuits 5 and 6. A first resistor R5, a second resistor R6 and a third resistor are connected between the input signal and a power supply having a predetermined voltage Vcc higher than the input signal.
A resistor R7 is connected in series in this order, and a resistor R8
is intervened. The other input terminal 9.1 of the comparator circuits 5 and 6
0 is commonly connected to the connection point 14 of the first and second resistors R5 and R6. A voltage Vcc is applied to the output terminal 11 of one comparison circuit 5. Connection point 1 between the 12 output terminals of the other comparator circuit 6 and the second and third resistors R6 and R7
Connected to 5. A capacitor C is connected to the connection point 14 to prevent malfunction of the comparator circuit 5.6 as described above.

FIG. 7 is a waveform diagram for explaining the operation of the embodiment shown in FIG. The signal waveform Fi of the output terminal 11 is shown in Fig. 7 (1), and the waveform of the input signal is shown in Fig. 7 (2).
is shown. Before time t1 when the output terminal 11 is at the high level VO)l, the output transistor 13 of the comparison circuit 5 is cut off, and similarly the output transistor included in the comparison circuit 6 is also cut off. The lower discrimination level VTLP when the input signal changes from low level to high level is expressed by the fifth equation.

During the period from time t1 to time t2 when the output terminal 11 is at a low level, all the output transistors 13 of the comparator circuit 5 are conductive, and the output transistor of the other comparator circuit 6 is also conductive. Therefore, there are 15 connection points and 6 comparison circuits.
is grounded to low level by the output transistor of . The upper discrimination level VTUP when the input signal changes from high level to low level is as shown by the sixth equation.

Compare this fifth formula with the prior art of the third formula.

The resistor R4 in the prior art is replaced by (R6
+R7). Therefore, the third and fifth equations
Comparing the equations, the noise margin associated with the lower VTLP ΔV3. ΔV4 (See Figures 4 and 7)Fi
are the same.

By comparing the fourth and sixth expressions expressing the upper discrimination level VTUP, the noise margins ΔVl and Δ■2 of the prior art are determined.
It is clear that the noise margin Δv5 according to this embodiment is larger than that of . In this way, the discrimination levels VTLP and VTUP are automatically set according to fluctuations in the voltage vS of the input signal, and an appropriate relatively large noise margin can be obtained according to the amplitude level of the input signal. Therefore, it is possible to reproduce a binary signal with less distortion and an accurate pulse width.

As described above, according to the present invention, the discrimination level is automatically set in accordance with fluctuations in the level of the input signal.

Moreover, its noise margin is large, so it is less distorted.
A value signal can be reproduced.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram of the prior art, FIG. 2 is a waveform diagram for explaining the operation of the prior art shown in FIG. 1, FIG. 3 is an electrical circuit diagram of another prior art, and FIG. 4 is a waveform diagram for explaining the operation of the prior art shown in FIG. 3, FIG. 5 is an electric circuit diagram of an embodiment of the present invention, and FIG. The circuit diagram and FIG. 7 are waveform diagrams for explaining the operation of the embodiment shown in FIG. 5.6... Comparison circuit, 7, 8; 9, 10... Input terminal, 11.12... Output terminal, R1-R8... Resistor, 13... Output transistor Figure 1, Figure 3 Figure 7

Claims (1)

[Claims] An input signal is commonly applied to one input terminal of a pair of open collector comparison circuits, and a first, second and third resistors are connected in series in this order, the other input terminal of the comparator circuit is commonly connected to the connection point of the first and second resistors, the output terminal of one comparator circuit is applied with the voltage, and the other A waveform shaping circuit characterized in that an output terminal of the comparison circuit is connected to a connection point between the second and third resistors.