JPS5910058A - Signal processor - Google Patents

Abstract

PURPOSE:To assure the decision for presence or absence of a signal to be detected if the noise is incorporated in an input signal, by providing a deciding circuit which extracts the output signal of a memory and then decides the presence or absence of a signal for each prescribed detecting period. CONSTITUTION:The prescribed reference value is supplied to a comparator 22 from a reference value setting circuit 23, and this reference value is compared with the count value. Here the reference value is set at ''4'' for example. Then the comparator 22 delivers a signal of level ''1'' when the count value exceeds the reference value. This signal is supplied to a memory 17 together with a writing pulse signal corresponding to a detecting signal ID and stored in response to the detecting period. The several period components are read out and supplied to a deciding circuit 18 for the signal stored in the memory 17. The circuit 18 decides the presence or absence of a signal obtained in a prescribed detecting period. That is, when the output signal level of the memory 17 is set at ''1'' in a certain period, the ''presence'' of a signal is decided for the corresponding period.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention is applicable to, for example, FSK (Frequency Sh
The present invention relates to a device for detecting inconsistencies in temporally separated signals such as (iftKeying) signals.

[Technical hell of inventions and their problems]

Figure 1 shows the signal processing device of Zokuchi.The horn is reception 1.
This is a receiver that converts No. 8 to frequency 7 and then detects it. The output signal of this receiver 11, for example, an FSK signal, is shown in FIG.
), signals of different frequencies corresponding to a predetermined seasonal issue are divided into sections for each chest period T, and this signal is also supplied to the foot circuit 12 at different levels. A reference signal Sh is supplied from a reference signal generation circuit 13 to the average determination circuit 12, and signals exceeding the reference signal Sh are extracted. The output signal of this level judgment circuit 12 (Kane 3
The diagram (shown in bl) is supplied to the waveform shaping circuit 14, @3
, 3 and 1 (c). The output of this waveform shaping circuit 14! Luth signal d-flip
It is supplied to the flop (FF) circuit 15, and this NO! The flip-flop circuit 15 is set by Rusui No. 6. The flip-flop circuit 15 is also supplied with the output 1g of the detection period setting circuit 16 as a set 48. This detection period setting circuit 16 is shown in FIG.
) A detection signal engineer having a detection period TD that matches the signal period T shown in ). The flip-70 horn circuit 15 is periodically reset by this detection signal ID. That is, this flip-flop circuit 15 is set by the first pulse signal in the signal period T, and is reset every signal period T. The set output signal (“1” level signal) of this flip-flop circuit 15 is the write pulse signal (FIG. 3 (f)) corresponding to the detection signal ID.
) is supplied to the memory 17 along with the detection period T
, is stored in correspondence with . Several cycles of the signal stored in the memory 17 are read out and supplied to the determination circuit 18.
This determination circuit 18 determines the presence or absence of the detected signal in a predetermined detection cycle. That is, if the output signal of the memory 17 is at the "1" level in a certain period, it is determined that the signal is present in that period, and if the output signal of the memory 17 is 0 and R, it is determined that there is no signal in that period. be done. This determination output signal is supplied to a subsequent stage circuit (not shown), and the negative sign of the detected signal is determined based on this determination output signal.

Incidentally, it is set according to the input signal level It of the reference signal generation circuit 13d.

According to the upper rudder configuration, it is possible to determine the presence or absence of a detected signal. However, in this configuration, the flip-flop circuit 15 is set by the first e-rus signal in the signal period T. Therefore, the third
Even if the signal includes noise at the end of the period Tn, such as the signal shown at period Tn in Figure (a), if the first part exceeds the reference signal Sh, the flip-flop circuit 15 is set. Therefore, it has the drawback of determining the piece as having a signal.

[Purpose of the invention]

This invention was made based on the above-mentioned rudder situation, and its purpose is to enable the EJ function to reliably determine the presence or absence of a detected signal even when the input signal contains grain content. The purpose of this invention is to provide a signal processing device with a high level of functionality.

[Summary of the invention]

This invention was designed to remove insects from the input signal! By counting the number of signals in each detection cycle and comparing this number with a reference value, it is determined whether the detected signal is insignificant within the detected group.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
I will clarify. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and only the different parts will be described.

In FIG. 2, the output of waveform shaping 1, 1, and 9 pulses is applied to a counter 2, and the counter 21 calculates the number il. This counter 2I is supplied with one detection signal having a detection period TD that coincides with the signal period T from the detection period setting circuit 16, and the counter 2I can be reset periodically by VC based on this detection signal. That is,
The output pulse signal of the waveform shaping circuit 14 is the third one, the first one is
In the case shown in (c), in the counter 21, 1F1
As shown in FIG.
[A certain reference value is supplied, and this reference value is compared with the weight value.] If the reference value is set to 4'', for example, the comparison circuit 22 outputs a "1" level signal as shown in FIG. 3(e) when the counted value exceeds this reference value. It is supplied to the memory 17 together with the convolution pulse signal (shown in FIG. 3(f)) corresponding to the signal ■D, and is stored in correspondence with the detection period. The signal is read out and supplied to the determination circuit 18, and the presence or absence of the signal in a predetermined detection cycle is determined in the determination circuit 18. That is, if the output signal of the memory 17 is at the "1" level in a certain cycle, The period is "there is a signal", and the output signal of the memory 17 is "
If the level is 0'', the period is determined to be "absent".

Note that the reference value setting circuit 23 is set based on the signal period T of the input signal.

According to the above configuration, the number of sets of pulse signals generated from the human input signal is set for each detection period, and the number of sets is 1lly.

The presence or absence of the detected signal within the detection period is determined by comparing the value with the reference value. DI, signal level and signal length (signal period) information %1'5c are used to determine the presence or absence of a signal. Therefore, even if the input signal contains 'C' noise, the level of the input signal is first judged, its movements are counted, and if this count is less than the standard value, it is determined that there is no signal. , it is possible to reliably determine the presence or absence of an enemy detection code.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a signal processing device that can reliably determine the presence or absence of a signal to be detected even when noise is included in the input signal.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing an example of a conventional signal processing device;
The figure is a block diagram showing one embodiment of the signal processing device according to the present invention, and FIG. 3 is a diagram shown to explain the operation of FIG. 1 and FIG. 2. ...Receiver, I2 ・Level judgment circuit, 13...
Reference signal generation circuit, 14 Waveform shaping circuit, 16 Detection layer Representative i1+ Patent Attorney Suzue Takehiko Figure 1 Old Figure 2 13
23fu11 Silkworm
Groove 11 12 14 21 2 1 to 0 times Counter polishing Figure 3 Commissioner of the Patent Office Kazuo Wakasugi 1. Indication of the case Patent application No. 117914/1983 2 Name of the invention Signal processing device: (, Relationship with the name neutrality that makes Ura 11- Patent issued I Yorito (307) Tokyo Shibaura'tunkei Co., Ltd. 11, Agent October 26, 1981 6, ?1li11- χ・] Elephant 7, the statement of contents of the amendment @ page 7, line 19 states, ``...Figure 3 (a+ to (
f) is...”? ``...Figure 3 is...'' he paused.

Claims (1)

[Claims] a receiver for detecting the received (N) signal; a circuit for determining the level of the output signal of the receiver in accordance with a predetermined reference E; and a circuit for shaping the waveform of the level-determined signal;
A counter that counts this waveform-shaped signal every predetermined detection period, a comparison circuit that compares the count value of this counter with a preset base value, What is claimed is: 1. A signal processing device comprising: a memory for storing data corresponding to a signal; and a determination circuit for extracting an output signal from the memory and determining the presence or absence of the signal at each of the predetermined detection cycles.