JPS5898942A - Forming method for ultrafine pattern - Google Patents
Forming method for ultrafine patternInfo
- Publication number
- JPS5898942A JPS5898942A JP19680181A JP19680181A JPS5898942A JP S5898942 A JPS5898942 A JP S5898942A JP 19680181 A JP19680181 A JP 19680181A JP 19680181 A JP19680181 A JP 19680181A JP S5898942 A JPS5898942 A JP S5898942A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- film
- etching
- etched
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 21
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000000992 sputter etching Methods 0.000 abstract description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 238000009413 insulation Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- -1 Phospho Chemical class 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
発明の利用分野
本発明は、マスクパターンの輪郭部に超微細パターンを
形成するエツチング方法とこれを用いたシリコン素子の
絶縁分離方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an etching method for forming an ultra-fine pattern on the contour of a mask pattern, and a method for insulating and isolating silicon elements using the etching method.
従来技術
半導体製造プロセスにおける微細パターンの形成法とし
てホトエツチング法が用いられて吟る。Photoetching is used as a method for forming fine patterns in conventional semiconductor manufacturing processes.
最近ではレジストの露光方法としてX線露光や電子線露
光が使用され1μm以下のパターンが形成されるように
なったが、0.1μm以下の超微細パターンは実現困難
である。Recently, X-ray exposure and electron beam exposure have been used as resist exposure methods to form patterns of 1 μm or less, but it is difficult to realize ultra-fine patterns of 0.1 μm or less.
発明の目的
本発明は1μm以下0.01μm程度までの超微細パタ
ーンが実現できる新規なパターン形成法を提供すること
を主な目的とする。OBJECTS OF THE INVENTION The main object of the present invention is to provide a novel pattern forming method that can realize ultra-fine patterns of 1 μm or less to about 0.01 μm.
発明の総括説明
すなわち、本発明は、第1のマスクパターン(例えば窒
化膜)の側面にのみ第2のパターンとなる膜(911え
は酸化@]を残すエツチング工程と、前記第2のパター
ンとなる膜を侵して、前記第1のマスクパターンを除去
する工程と、前記残した第2のパターンとなる膜をエッ
チングマスクトシて、下地材料をエツチングする工程と
から成るパターン形成法である。General description of the invention That is, the present invention includes an etching process that leaves a film (911, oxide) that will become a second pattern only on the side surface of a first mask pattern (for example, a nitride film); This pattern forming method consists of the steps of removing the first mask pattern by attacking the film that will become the second pattern, and etching the underlying material by using the remaining film that will become the second pattern as an etching mask.
以下、本発明を実施例を参照して詳細に峠明する。Hereinafter, the present invention will be explained in detail with reference to Examples.
実施例1
第1図は本発明による3i基板のエツチング工程を示し
たものである。Si基板1上に窒化膜(Si3N4)の
パターン2をホトエツチングによって形成し、酸化5(
stottaを堆積してビ)図に示した形状を得る。こ
こで窒化@2のエツチングはフレオンガスを用いた反応
性スパッタエツチングで行い窒化膜パターンの側面は垂
直にしておき、酸化膜3の堆積はCV D (Chem
jcalyapour peposition )
によって等方的に膜を形成しておく。続いて、フレオン
ガスを用いた反応性スパッタエツチングで酸化膜3を膜
厚分だけサイドエツチングなしにエツチングすると(口
]に示すように窒化膜パターン2の側面にのみ酸化膜の
エツチング残り4を形成することができる。こうした後
に窒化膜5 t−IJフッ酸除去すると酸化膜のエツチ
ング残り4は超微細なパターンとなって残る。この酸化
膜4をマスクとして3i基板をエツチングすると、el
に示すように超微細なSiパターン6を得る。上記81
基板のエツチングにはCCZ、とOlの混合ガスを用い
た反応性スパッタエツチング法などを用いれば酸化膜パ
ターン4の寸法通りにBrをエツチングできる。Example 1 FIG. 1 shows the etching process of a 3i substrate according to the present invention. A pattern 2 of a nitride film (Si3N4) is formed on a Si substrate 1 by photoetching, and an oxide film 5 (
B) Obtain the shape shown in the figure by depositing stotta. Here, the etching of nitride@2 is performed by reactive sputter etching using Freon gas, the side surfaces of the nitride film pattern are kept vertical, and the deposition of oxide film 3 is performed using CVD (Chem.
jcalyapour peposition)
A film is formed isotropically. Next, by reactive sputter etching using Freon gas, the oxide film 3 is etched by the film thickness without side etching, so that the remaining oxide film 4 is formed only on the sides of the nitride film pattern 2, as shown in (). After this, when the nitride film 5 is removed with t-IJ hydrofluoric acid, the etched oxide film 4 remains as an ultra-fine pattern.When the 3i substrate is etched using this oxide film 4 as a mask, el
An ultrafine Si pattern 6 is obtained as shown in FIG. 81 above
When etching the substrate, Br can be etched according to the dimensions of the oxide film pattern 4 by using a reactive sputter etching method using a mixed gas of CCZ and OI.
上記のエツチングでは最初の窒化膜パターンの輪郭部す
べてに超微細パターンが形成さ扛るが、酸化膜の超微細
パターン形成後ホトエツチングによって不要な酸化膜パ
ターンを除去してからSiエツチングを行うことももち
ろん可能である。In the above etching, an ultra-fine pattern is formed on all the contours of the initial nitride film pattern, but after the ultra-fine pattern of the oxide film is formed, unnecessary oxide film patterns can be removed by photo-etching, and then Si etching can be performed. Of course it is possible.
実施例2
第2図は本発明によるSi基板の櫛状のエツチング工程
である。まず(イ]に示すように酸化膜(8iot)パ
ターン11の側面に実施例1と同様にして窒化[1(S
’3N4 ) の微細パターン12を残す。酸化膜
11をフッ酸溶液で除去した後、再度同様の工程を繰返
して、(ロ)に′示す1つに酸化膜の微細パターン13
を残す。この酸化膜をマスクにしてSiをエツチングす
るとeS)に示すような櫛状に並んだBiパターン14
を得る。Embodiment 2 FIG. 2 shows a comb-shaped etching process of a Si substrate according to the present invention. First, as shown in (A), the side surface of the oxide film (8iot) pattern 11 is coated with nitride [1(S)] in the same manner as in Example 1.
'3N4) fine pattern 12 is left. After removing the oxide film 11 with a hydrofluoric acid solution, the same process is repeated again to form a fine pattern 13 of the oxide film as shown in (b).
leave. When Si is etched using this oxide film as a mask, a Bi pattern 14 arranged in a comb shape as shown in eS) is formed.
get.
第3図は上記の櫛状B+パターンを用いた3i素子の絶
縁分離工程でるる。まず、(イ)に示すように、Si基
板上全面に上記方法によって縞状に酸化膜(Sift)
微細バター721を配置した後、その上にホトレジスト
でf3i素子のパターン22を配置する。続いてSi基
板をエツチングすると(ロ)に示すようにSi素子パタ
ーン23以外のところKは櫛状の断面形状をもった3i
パターン24が形成される。こうした後、ホトレジス1
−2zおよび酸化膜を除去して、櫛状の81t’4E全
にSin!に変換できるまで熱酸化を行うと、elに示
すように熱酸化による体積膨張のためsho、で充填さ
れた絶縁分離領域25を形成することができる。なお、
ここで櫛状のSiパターン幅とその間隔の比を9対11
とすればほぼ平坦な絶縁分離領域を形成できる。FIG. 3 shows the insulation isolation process of a 3i element using the above-mentioned comb-shaped B+ pattern. First, as shown in (a), an oxide film (Sift) is formed in stripes on the entire surface of the Si substrate by the above method.
After placing the fine butter 721, the f3i element pattern 22 is placed thereon using photoresist. Subsequently, when the Si substrate is etched, as shown in (b), except for the Si element pattern 23, K is 3i with a comb-shaped cross-section.
A pattern 24 is formed. After doing this, Photoregis 1
-2z and the oxide film are removed, and the entire comb-shaped 81t'4E is Sin! When thermal oxidation is carried out until it can be converted to sho, an insulating isolation region 25 filled with sho can be formed as shown in el due to volume expansion due to thermal oxidation. In addition,
Here, the ratio of the comb-shaped Si pattern width to its spacing is 9:11.
By doing so, a substantially flat insulation isolation region can be formed.
第4図は櫛状のSiパターン幅をその間隔に比べ非常に
小さくした場合の絶縁分離構造である。FIG. 4 shows an insulation isolation structure in which the width of the comb-shaped Si pattern is made much smaller than the spacing thereof.
3iパタ一ン幅が小さいため熱酸化膜31を形成した後
も絶縁分離領域が充填されず、引き続きsio、(ま九
1d8i、N4.Po1)’Si )32を堆積して充
填を行う。この場合、櫛状のSiパターン幅を小さくし
たことによって無端化ll31を薄くすることができ、
素子形成儂域33への酸化膜の食い込み量を低減できる
。また、堆積膜32による絶縁分離領域の充填において
は、櫛状の3i0゜34が溝を分割しているため、櫛状
のsio、かない場合よりも溝を充填する堆積膜32を
薄くすることができ、したがって充填後の平坦V+内向
上る。Since the width of the 3i pattern is small, the insulation isolation region is not filled even after the thermal oxide film 31 is formed, and sio, (1d8i, N4.Po1)'Si) 32 is subsequently deposited and filled. In this case, by reducing the width of the comb-shaped Si pattern, the endless layer 1131 can be made thinner.
The amount of penetration of the oxide film into the element formation region 33 can be reduced. Furthermore, in filling the insulation isolation region with the deposited film 32, since the comb-shaped 3i0°34 divides the trench, it is possible to make the deposited film 32 filling the trench thinner than in the case where there is no comb-shaped sio. Therefore, the flat V+ after filling increases.
以上説明したように、本発明に工nば堆積膜厚によって
0.01μm程度の精度で超微細パターンを形成するこ
とができる。また、Siの超微細パターンを櫛状に形成
すると、熱酸化のみまたはその上に堆積膜を形成して容
易に平坦な絶縁分離領域を形成することができる。As explained above, by applying the present invention, ultra-fine patterns can be formed with an accuracy of about 0.01 μm depending on the thickness of the deposited film. Furthermore, if an ultra-fine Si pattern is formed in a comb shape, a flat insulating isolation region can be easily formed by thermal oxidation alone or by forming a deposited film thereon.
なお、本発明の超微細パターン形成法は種々の下地材料
に適用することができる。例えば、下地材料としてpo
lyst、 stへ* 8’MNa e A’を選
べば、こnらのエツチングマスクとなる材料を堆積膜に
選んで実施PI 1の工程を行うことができ為。Note that the ultrafine pattern forming method of the present invention can be applied to various base materials. For example, as a base material, po
lyst, to st* If you select 8'MNa e A', you can perform the process of PI 1 by selecting these etching mask materials for the deposited film.
また、下地材料に凹凸のめるような場合に1、リンガラ
X (phospho 5ilicate Qlass
)等の流動できる材料でいったん平坦化してリンガラ
ス等に超微細パターンを形成した後さらに下地にそのパ
ターンを転写するようにエツチングを行えばよい。In addition, when applying unevenness to the base material, 1. Phospho 5ilicate Qlass
), etc., to form an ultra-fine pattern on the phosphor glass, etc., and then etching is performed to transfer the pattern to the base.
第1図は本発明のエツチング工程を示す断面図、第2図
は本発明の櫛状エツチング工程を示す断面図、第3図は
本発明の絶縁分離工程を示す断面図、第4図は絶縁分離
構造例の断面図である。
l・・・Si基板、2.5・・・窒化膜、3・・・酸化
膜、4V]Z 図
¥J 1 図
貰 3 9
乃JJ じコFIG. 1 is a cross-sectional view showing the etching process of the present invention, FIG. 2 is a cross-sectional view showing the comb-like etching process of the present invention, FIG. 3 is a cross-sectional view showing the insulation separation process of the present invention, and FIG. FIG. 3 is a cross-sectional view of an example of a separation structure. 1...Si substrate, 2.5...Nitride film, 3...Oxide film, 4V]Z Figure ¥J 1 Figure 3 9 乃JJ Jiko
Claims (1)
ンとなる膜を残すエツチング工程と、前記第2のパター
ンとなる膜を聾して前記l!1のマスクパターンを除去
する工程と、前記残した第2のパターンとなる膜をエツ
チングマスクとして下地材料をエツチングする工程とか
ら成ることを特徴とする超微細パターンの形成法。1. An etching process that leaves a film that will become the second pattern only on the side surface of the first mask pattern; 1. A method for forming an ultra-fine pattern, comprising the steps of: removing a first mask pattern; and etching a base material using the remaining film forming the second pattern as an etching mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19680181A JPS5898942A (en) | 1981-12-09 | 1981-12-09 | Forming method for ultrafine pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19680181A JPS5898942A (en) | 1981-12-09 | 1981-12-09 | Forming method for ultrafine pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5898942A true JPS5898942A (en) | 1983-06-13 |
Family
ID=16363869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19680181A Pending JPS5898942A (en) | 1981-12-09 | 1981-12-09 | Forming method for ultrafine pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5898942A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4847183A (en) * | 1987-09-09 | 1989-07-11 | Hewlett-Packard Company | High contrast optical marking method for polished surfaces |
EP0346535A1 (en) * | 1987-02-27 | 1989-12-20 | BRITISH TELECOMMUNICATIONS public limited company | Self-aligned bipolar fabrication process |
US4927774A (en) * | 1988-06-10 | 1990-05-22 | British Telecommunications Plc | Self aligned bipolar fabrication process |
JPH0362946A (en) * | 1989-07-31 | 1991-03-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JP2004528732A (en) * | 2001-06-05 | 2004-09-16 | ナショナル ユニバーシティ オブ シンガポール | Power MOSFET with enhanced breakdown voltage |
JP2006100825A (en) * | 2004-09-29 | 2006-04-13 | Agere Systems Inc | Thick oxide region in semiconductor device and its forming method |
JP2009246189A (en) * | 2008-03-31 | 2009-10-22 | Citizen Finetech Miyota Co Ltd | Method of manufacturing semiconductor substrate, semiconductor substrate, and piezoelectric device using semiconductor substrate |
JP2010503206A (en) * | 2006-08-30 | 2010-01-28 | マイクロン テクノロジー, インク. | Single spacer process for multiple pitch multiplication and related intermediate IC structures |
-
1981
- 1981-12-09 JP JP19680181A patent/JPS5898942A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0346535A1 (en) * | 1987-02-27 | 1989-12-20 | BRITISH TELECOMMUNICATIONS public limited company | Self-aligned bipolar fabrication process |
US4847183A (en) * | 1987-09-09 | 1989-07-11 | Hewlett-Packard Company | High contrast optical marking method for polished surfaces |
US4927774A (en) * | 1988-06-10 | 1990-05-22 | British Telecommunications Plc | Self aligned bipolar fabrication process |
JPH0362946A (en) * | 1989-07-31 | 1991-03-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JP2004528732A (en) * | 2001-06-05 | 2004-09-16 | ナショナル ユニバーシティ オブ シンガポール | Power MOSFET with enhanced breakdown voltage |
JP2006100825A (en) * | 2004-09-29 | 2006-04-13 | Agere Systems Inc | Thick oxide region in semiconductor device and its forming method |
JP2010503206A (en) * | 2006-08-30 | 2010-01-28 | マイクロン テクノロジー, インク. | Single spacer process for multiple pitch multiplication and related intermediate IC structures |
JP2009246189A (en) * | 2008-03-31 | 2009-10-22 | Citizen Finetech Miyota Co Ltd | Method of manufacturing semiconductor substrate, semiconductor substrate, and piezoelectric device using semiconductor substrate |
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