JPS5898813A - Reproducing device for digital signal - Google Patents

Abstract

PURPOSE:To eliminate erroneous pulses, by gating the detection signal of a frame synchronizing signal by gate pulses having a window width where the length of time of generation of cycle slip is taken into consideration. CONSTITUTION:A reproduced PCM audio signal from an input terminal 1 is supplied to a frame synchronizing signal detecting circuit 22. A frame synchronizing signal detected in this circuit 22 is supplied to a gate circuit 23. The detection signal of the frame synchronizing signal obtained through the gate circuit 23 is supplied to an OR gate 25 and a clear terminal of a counter 26. The counter 26 counts clock pulses from a clock generator 27. The output of the counter 26 is inputted to an N-''3'' (bit) detector 28 and a ''3'' (bit) detector 29, and a flip-flop circuit 30 is set or reset by outputs of these detectors 28 and 29. The output of the flip-flop circuit 30 and the output of a counter 31 are supplied to the gate circuit 23 through an OR gate 24.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a compensation circuit for a frame synchronization signal (block synchronization signal) of a reproducing device for a digital signal recorded in a baseband that is not based on a carrier modulation method such as AM modulation or FM modulation. Regarding.

For example, an apparatus is known in which an audio signal is converted into digital PCM and recorded on a disc, and the recorded digital PCM audio signal is reproduced from the disc. In the case of this PCM audio disc recording/playback device, when recording a PCM audio signal, A
A baseband recording method is used that does not rely on carrier modulation methods such as M modulation or FM modulation. And in this case, the run length limited code (run l
engtlimited code ) modulation method is used. This modulation method uses two data transitions for 0” or °゛1” data.
The purpose is to increase the recording efficiency by increasing the minimum inversion interval between the two, and to shorten the maximum inversion interval to facilitate self-clocking on the reproduction side.

By the way, when recording and reproducing a digital signal, in order to facilitate error correction and other processing of the digital signal, a plurality of samples are divided into blocks, and each block is processed.

The length of one block is treated as one frame period on a digital audio disc. And this one
A frame synchronization signal (block synchronization signal) is inserted at the beginning of each block of data to mark each block.

In this case, the frame synchronization signal is a bit pattern with two consecutive maximum inversion intervals, that is, an interval of "1", taking advantage of the fact that a modulated output with consecutive maximum inversion intervals does not appear in normal modulation. A pattern is used as a frame synchronization signal in which a period of "0" continues for the maximum reversal interval, followed by a period of "0" for the maximum reversal interval.

As mentioned above, this frame synchronization signal is detected on the playback side, and the subsequent data is processed appropriately based on the detection of this frame synchronization signal, but for the following reasons, this frame synchronization signal In some cases, the signal may not be detected correctly, so a frame synchronization signal compensation circuit is generally provided on the playback side.

That is, for example, a frame synchronization signal may be lost due to a scratch on the disc.

Furthermore, pulse-like noise similar to a frame synchronization signal may be mixed into the reproduced signal, and this may be erroneously reproduced as a frame synchronization signal, resulting in errors in subsequent processing. Furthermore, while a frame synchronization signal is not detected during a search mode such as finding the beginning of an audio signal, if a frame synchronization signal is not obtained immediately after this search mode ends, the search mode will switch to normal playback mode. This also means that it will take some time to obtain a stable reproduced signal.

The period of the frame synchronization signal may change due to various other causes, and it is also necessary to correct this.

As a compensation circuit for such a frame synchronization signal, the one shown in FIG. 1 is conventionally known.

That is, in FIG. 1, the reproduction P through the input terminal (1)
CM audio data (NRZ data) is stored in register (2
). This register (2) has the number of stages of n bits corresponding to the length of the frame synchronization signal.
The n-bit parallel data is supplied to the frame synchronization signal detection circuit (3) by this register, and detected by matching the frame synchronization signal covert of the bit pattern described above.

In addition, the output of this register (2) is supplied to the memory (4) for one block of data, and within one frame period,
That is, all data for one block is written to this memory. When all data for one block is written into this memory, each data is supplied from this memory to the register (5).

That is, data delayed by one frame period is obtained from the memo 'J-(4), and this is supplied to the register (5). This register (5) is also register (2)
Similarly, it has n-bit stages, and n-bit parallel data is supplied to the frame synchronization signal detection circuit (6).

A frame synchronization signal is detected in the same manner as described above.

Furthermore, the output of this register (5) is supplied to a memory (7) for one block of data, delayed by one frame period, and then supplied to a register (8). This register is also similar to registers (2) and (5), and n-bit parallel data from this register is sent to the frame synchronization signal detection circuit (
9), and a frame synchronization signal is detected with a delay of two frame periods relative to the input data.

And these frame synchronization signal detection circuits (3).

(Detection signal Fo of frame synchronization signal from 61, <91
, pl.

F2 is supplied to the majority logic circuit 00), and three signals F
o, F1. A majority logic is adopted here in which when the phases of the generation points of two or more of the signals F2 match, the matching points and the output signal FA are obtained. Three detection circuits (3) ensure that the disk rotation speed is stable and the frame synchronization signal is stable at the correct frame period.
When the output signals are obtained from (6) and (9), the phases of the output signals of the detection circuits (3), (6), and (9) match, and the output signals from the majority logic circuit 00) are always in the frame period. An output signal FA is obtained.

If two or more frame synchronization signals are missing in a row due to a dropout, the signals FO, F 1 , F 2 will no longer match the phases of the two or more signals at the time the dropout occurs, so this majority decision The output signal FA from the logic circuit 00) is no longer available at that point.

A clock pulse CP from a clock generator a3 is supplied to the clock terminal of the counter αB. And this counter (II) has one frame period, clock generator 03)
A carry pulse PCQ is generated by counting clock pulses CP from , and this carry pulse FC becomes a frame period signal. Therefore, even when a signal from majority logic circuit α0 cannot be obtained, that is, even when a frame synchronization signal with a correct period cannot be obtained, a signal with a frame period can be obtained from this counter αυ. If a frame synchronization signal with a correct period is obtained from the majority logic circuit α0), the counter aυ is reset by the frame synchronization signal, so that the carry pulse Fc also becomes a signal having exactly the same phase as the detected frame synchronization signal.

This carry pulse FC is supplied to the other input terminal of OR gate 02. Therefore, if the frame synchronization signal from the majority logic circuit 00) is correct, this frame synchronization is taken out as is from the OR gate 02).
The output carry pulse FC from the majority logic circuit (counter 01 when no signal is obtained from IQ+) due to dropout etc. is obtained from this to the output end side. .

Note that 05 is an output terminal for PCM audio data.

Let's further explain the operation of this circuit with reference to a time chart.

To obtain a reproduced digital signal, it is necessary to bit-synchronize the signal extracted from the disk using a clock signal synchronized with this signal, but in this bit synchronization circuit, there is a relative phase shift between the clock signal and the reproduced signal. When this is integrated, a cycle slip phenomenon occurs in which one cycle is missed or increased. In normal playback mode, the PL that constitutes the bit synchronization circuit
By selecting the frequency of the variable frequency oscillator of the L circuit and the time constant of the low-pass filter, the time error caused by cycle slip is suppressed to approximately ±1 to 2 bits.

FIG. 2 shows signals when the period of the frame synchronization signal shortens and when dropout occurs among the cycle slip phenomena.

That is, Fig. 2 A, B, and C show the output signals "Or" of the frame synchronization signal detection circuits (3), (61 and (9)).
1 and F2 are shown, respectively. The output signal Fo of the frame synchronization signal detection circuit (3) is a detection signal obtained by detecting the frame synchronization signal from the reproduced signal from the input terminal (1),
The output signal F1 of the frame synchronization signal detection circuit (6) is a signal delayed by one frame period, and
The output signal F2 of the frame synchronization detection circuit (9) is a signal that is further delayed by one frame period.

In this case, the period of the 3rd and 4th frame synchronization signals in FIG. It is.

1. The period marked with a circle in Figure 2 is the regular frame period,
The incorrect period is indicated by an X.

In this case, as is clear from FIG. 2, in the part where the cycle slip occurs, the output signal F'A of the majority logic circuit 0 is the fourth frame synchronization signal, as shown in the same figure. For the signal F1 from the frame synchronization signal detection circuit (6) and the frame synchronization signal (9)
is obtained at this point because the phase of the signal F2 from
Since the phase of signal F1 and signal F1 are the same, it is extracted at this point.

The counter Q] is determined by the output of this majority logic circuit α0)
) is reset, so a signal FC as shown in FIG. 5E is obtained from the counter (II). In Figure 2E, the signal of the 5th frame period is not obtained from the counter αυ because the length of the period between the 4th and 5th frames is shorter than the frame period, so the signal of the 5th frame period is carried from the 5th counter aυ. This is because the counter α1) is reset by the pulse from the majority logic circuit 00) before the pulse PC is obtained.

The OR gate output of the output FA of the majority logic circuit 00) and the output F'C of the counter αυ is provided at the terminal α (a), and the output signal FC of the frame synchronization signal as shown in FIG. In this case, it is clear from the figure that the frame synchronization signal for the dropout period is obtained by interpolating the frame period carry pulse obtained from the counter θ1).

FIG. 3 shows that a cycle slip occurs between the third frame synchronization signal and the fourth frame synchronization signal,
This is an example of a case where the length becomes longer than one frame period and a case where dropout occurs as described above.

In this case, the signals Fo, F1 . F2 is A and B in the same figure.
, C, respectively, and the signals FA, FC, F'G
are shown in the same figure, and E and F correspond to Fig. 2.

In this example, since the length of the cycle slip is longer than one frame period, the counter is not reset before the carry pulse is obtained at 0υ as in the example shown in Fig. As shown in E, a frame period carry pulse is obtained, and at a point in time between this obtained carry pulse and the next carry pulse, the counter (
11) is reset, the period in between corresponds to the cycle slip, that is, is larger than one frame period. Therefore, the signal FC obtained from terminal a4) VC becomes as shown in FIG.

FIG. 4 shows a case where noise in the reproduced signal is mixed as a pseudo frame synchronization signal, and when the reproduction device is in search mode and during this search mode, the frame synchronization signal detection circuits (3), (6), (9) This is a case in which a frame synchronization signal is not detected. Figure 4A.

B, C, E, and F represent the signals "O+Fl,"2, and FA, FC, and PC, respectively, as in FIGS. 2 and 3.

In this case, the pulse mixed as a pseudo synchronization signal is the signal Fo.
Since the generation positions of +Fl and F2 do not overlap with each other, the output signal FA of the majority logic circuit a2 is obtained with this pseudo synchronization pulse removed, as shown in the figure.

During a period in which a frame synchronization signal is not obtained because the playback device is in the search mode, signals of the frame period are sequentially obtained from the counter 0υ, and these signals are obtained at the terminal 04). After the search mode ends, the majority logic circuit α [
Since more output pulses F'A will be obtained, the counter αυ will be reset before the next carry pulse is obtained. Therefore, as shown in Figure E, this period is longer than one frame period, but a signal as shown in Figure F is obtained on the terminal side. In other words, a signal with the correct frame period is output immediately after the search mode ends.

As described above, a substantially correct frame synchronization signal can be obtained by compensating for abnormal situations such as cycle slips and search mode, or for dropouts and noises.

By the way, this conventional circuit requires a memory, and this memory must be fast. Also, since it uses a majority logic circuit, the pseudo frame synchronization pulse has the same period of each frame period. There is an inconvenience that it is not possible to eliminate the cases in which they are obtained continuously at certain positions.

This invention attempts to propose a circuit that can eliminate the above-mentioned drawbacks.

In this invention, the following points are taken into consideration.

In other words, ■The cycle slip that occurs in the reproduced signal is usually about ±1 or 2 bits, which is extremely small compared to the frame period, and ■The pattern of the frame synchronization signal is usually selected as a special pattern. , There should be a relatively safe area before and after the pattern detection for frame sync signal detection, ■ The frame sync signal pattern is often selected from a non-regular pattern based on the modulation method, and is random. In a data string, the probability of occurrence of the same pattern is 0 or very small unless there is dropout or a pseudo synchronization signal mixed in.

Hereinafter, an example of a frame synchronization signal compensation circuit according to the present invention will be explained with reference to the drawings.

FIG. 5 is an example of a system diagram of the compensation circuit according to the present invention, in which the reproduced PCM audio signal (
The frame synchronization signal detection circuit (NRZ data) is supplied to the frame synchronization signal detection circuit (2nd limit).This frame synchronization signal detection circuit (second limit ma) detects a signal with the same bit pattern as the frame synchronization signal from the data, as in the previous example. , this circuit (221
The frame synchronization signal detected in the gate circuit (2
: Supplied to Tsugo. The output signal of the OR gate (2 (A)) is supplied to this gate circuit (2 (8)) as a gate signal. In this case, the gate signal that is the output signal of the OR gate (2 (A)) is a normal The window pulse has a pulse width of about ±3 bits with respect to the position where the frame synchronization signal occurs. Therefore, when the frame synchronization signal is detected at the correct position by the detection circuit (2 times), the detection signal 8FO is this gate circuit (2
3).

The detection signal SF'w of the frame synchronization signal obtained through the gate circuit (23) is supplied to one input terminal of the OR gate (2) and also supplied to the clear terminal of the counter C0. is supplied with a clock pulse CP from a clock generator (5).

This clock generator is synchronized with the clock component of the reproduced signal, and uses, for example, a PLL circuit. Therefore, the counter (26) is configured to obtain a carry pulse SF'C having a frame period synchronized with the reproduced signal.

The frame period signal obtained from the counter (26) is then supplied to the other input terminal of the OR gate (25).

Note that the output clock of this clock generator (double output clock) is also used as a clock for frame synchronization signal detection.

The gate circuit (gate signal 231 ~ is this counter c!
6) is formed as follows based on the count value output.

That is, when the count value of the counter (26) becomes smaller than the count value N corresponding to the frame period by the maximum value of the cycle slip, for example, a number corresponding to 3 bits of data, this is detected by the detector (28), 7 lip flop circuits (to) are set by the detection output. When the counted value of the shuffled counter (26) reaches a value equivalent to 3 bits of data, it is detected by the detection circuit (c).
The detection output causes the flip-flop circuit to be reset. Considering that the counter (A) is cleared by the frame period signal SPW, the signal from the flip-flop circuit (7) rises at a position 3 pits before the position of the frame synchronization signal, and 3 bits from the position of the frame synchronization signal. A falling signal is obtained at a delayed time, and this is supplied to the gate circuit (c) as a gate signal through the OR game (04).

Note that if the frame synchronization signal and the output carry pulse SF'C of the counter (26) are out of phase, the detection signal 81''w of the frame synchronization signal cannot be obtained from the gate circuit e3). In this case, the counter (26) is forcibly cleared in the following manner so that the two phases match.

That is, 01) is a monitoring counter for detecting the state. The detection signal SPw of the frame synchronization signal obtained from the gate circuit (23) is supplied to the clear terminal of this counter t31), and the detector (
output pulses are supplied.

In this case, since the counter (26) always counts the clock pulse CP, a pulse is obtained from the detector CI'9) at the frame period, and this is counted by the counter G+
), but the gate circuit (23)
While the frame synchronization signal detection signal is being obtained from the counter (31), the frame synchronization signal detection signal SF'w is supplied to the clear terminal of the counter (31) at one frame period. It is cleared every time one pulse from (to) is counted, and the count value of this counter C31) does not increment. On the other hand, when the frame synchronization signal is no longer obtained from the gate circuit, this counter 1) is not cleared and counts the pulses from the detected Masuda.

When the count value reaches a predetermined number, for example "8", the output signal SI of the counter (31) becomes high level. This output signal sL is supplied to the enable terminal of this counter (C31).
3]) stops counting. This output signal SL is supplied to the gate circuit (24) through (24). In this case, the gate signal ~ is always at a high level, and the gate circuit C3) is in an open state. Then, the pulse from the frame synchronization signal detection circuit (22) is transmitted to this gate circuit (
23), the counter cI) of and is cleared, its output signal sL falls to a low level, and the counter Gυ of and returns to a countable state.

In other words, the output carry pulse SFC of the counter (26)
When the phase of the frame synchronization signal in the reproduced signal is largely shifted and the detection signal of the frame synchronization signal does not enter within the window pulse Pw, this is detected by the monitoring counter c31), and the counter c! This counter (26) is cleared so that the phase of the output carry pulse SFC in step 6) matches the frame synchronization signal position of the reproduced signal.

The operation of the circuit shown in FIG. 5 will be further explained with reference to the time chart as in the case of the conventional example described above.

FIG. 6 corresponds to FIG. 2 and is an example of operation when a period shorter than one frame period occurs due to cycle slip and when dropout occurs. A in the figure is the output SFo of the frame synchronization signal detection circuit 0, B is the output Pw of the OR gate (2), and C is the output SPw of the gate circuit C23). (A) is the output carry pulse SFC, and E in the same figure is the OR gate (two output SFG).As is clear from this figure, when a cycle slip that is shorter than the frame period occurs, the window pulse Although the width is shortened as shown in FIG. 2B, if it is within -3 bits from the normal frame synchronization signal position, a detection pulse can be obtained from the gate circuit C23). In other words, since the cycle slip is at most ±3 bits, the detection signal of the frame synchronization signal is sent to the gate circuit (23).
This is something that can be obtained more easily.

Here, the counter (A) is cleared by the pulse at this point before the carry pulse SFC is generated, so the output carry pulse SFc of this counter (26) is as shown in the figure, when this cycle slip occurs. It will be missed for a period of time.

On the other hand, when a dropout occurs, there is no frame synchronization signal within the window pulse width of the gate signal ~, so no frame synchronization signal appears at the output of the gate circuit. Since the counter (26) is correctly cleared by the detection signal, the output carry pulse SFC of the counter (to) becomes a signal with a correct frame period, and this is taken out as the signal SF'G through the OR gate.

FIG. 7 similarly shows a case where a cycle slip and a dropout occur, and this example is a case where the period becomes longer than the frame period due to the occurrence of a cycle slip. In this case, the counter (26) has a carry pulse S
After generating F'C, it is cleared by the signal SPw obtained from the gate circuit (23+, so the length of the period after this cycle slip occurs will be different from the normal one.However, it is an or game) & The output of ■ is E in the same figure.
It will look like the one shown below.

FIG. 8 shows a case where a pseudo synchronization pulse is mixed in, and a case where a frame synchronization signal is absent for a long period of time due to the playback device being set to search mode.

In this case, since it is extremely rare for a pseudo synchronization pulse to fall within the window pulse width, a frame synchronization signal detection signal is obtained from the gate circuit (c) with this pseudo synchronization pulse removed. On the other hand, during the search mode period in which no frame synchronization signal is obtained from the frame synchronization signal detection circuit @, when the monitoring counter C31) detects that there is no frame synchronization signal for 8 frames, this counter Gυ output signal ST, (Fig. 8F
), the gate circuit (23) is set to an open state, and the frame synchronization signal detected by entering the normal mode after the search mode is gated by the gate circuit (23). When [F] is cleared, the counter C26) is also cleared. Therefore, as shown in the figure, although the output pulse SFc of the counter 12 becomes slightly discontinuous after the search mode, a signal with the correct frame period can be obtained thereafter.

As described above, according to the present invention, it is possible to realize a frame synchronization signal compensation circuit with a simple configuration without using a memory with a large capacity as in the prior art.

In addition, since the frame synchronization signal detection signal is gated by a gate pulse with a window width that allows for the time required for a cycle slip to occur, an erroneous pulse at the same position within each frame period is detected by the frame synchronization signal detection circuit. Even if a pulse is obtained, the effect is that the erroneous pulse can be removed.

It should be noted that the present invention is of course applicable not only to a reproducing apparatus for a digital PCM audio disc, but also to a compensation circuit for detecting a block synchronization signal or the like when baseband recording a digital signal.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an example of a conventional frame synchronization signal compensation circuit, FIGS. 2, 3, and 4 are time charts for explaining the same, and FIG. 5 is a system diagram showing an example of a conventional frame synchronization signal compensation circuit. A system diagram of an example of the compensation circuit, and FIGS. 6, 7, and 8 are time charts for explaining the system. Figure 1

Claims (1)

[Claims] 1. The data is modulated with a run-length limited code and divided into blocks for each unit of time, and a bit pattern that does not appear in the normal modulation of the run-length limited code is synchronized with the data in each block. A device for reproducing a digital signal added as a signal, comprising: a detection circuit that detects the synchronization signal from the reproduced digital signal; and a gate that gates the detection signal of the synchronization signal from the detection circuit. and a window pulse forming circuit that forms a window pulse having a pulse width for a certain period before and after the time point at which the synchronization signal is obtained, based on the output signal of the gate circuit, and the window pulse is A digital signal reproducing device, wherein the gate signal of the gate circuit is used to open the gate circuit during the pulse width section. 2. A state in which the data is modulated with a run-length limited code and divided into blocks for each unit of time, and a bit pattern that does not appear in the normal modulation of the run-length limited code is added to the block unit data as a synchronization signal. A device for reproducing a digital signal, comprising: a detection circuit for detecting the synchronization signal from the reproduced digital signal; a gate circuit for gating the detection signal of the synchronization signal from the detection circuit; Based on the output signal, a window pulse having a pulse width for a certain period before and after the time point at which the synchronization signal is obtained is formed, and this window pulse is supplied to the gate circuit to generate a gate signal on the pulse width section. A window pulse forming circuit that is opened, and a frame period signal that is cleared by the output signal of the gate circuit and obtained from the window pulse forming circuit are counted as a clock, and the count value exceeds a set value. and a monitoring circuit for forcibly opening the gate circuit to correct the phase shift of the window pulse from the phase of the frame synchronization signal of the reproduced digital signal.