JPS5897184A - Address translation method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus equipped with an address translation mechanism, and particularly to an address translation method.

Currently, most computers are configured with 24 bits as logical addresses, and are generally capable of creating addresses of up to 16 MB. In recent years, for such calculators,
The shortage of logical addresses is becoming noticeable.

For example, in the field of scientific and technical computing, the amount of data required for matrix operations and the like has increased, and in many cases it does not fit into the 16 MB address space. In such cases, the current countermeasure is to use an external device such as a magnetic disk, but as the calculation speed of processing devices has improved significantly, data transfer between the external device and the main storage device has become more difficult. Even if a processing device with high calculation speed is used, the overall
The performance of the buoy may not improve much. For this reason,
There is a growing demand for matrix data etc. to reside in the main memory and to be referenced/updated by direct commands.

Against this background, there is a need to expand logical addresses, but a method that is an extension of the current method is to expand logical addresses to approximately i52 bits and convert them to real addresses through an address translation mechanism. It will be done.

However, unlike conventional programs, the answer to the logical address area of 16MB or more is different from that of conventional programs.9 For example, there is a lot of special data such as matrix data, so instead of using the general method described above, we have to take these specialities into account. It is thought that this method would be more efficient. Such areas generally have the following characteristics:

(1) Data in this area is intensively referenced/updated only during a certain period of time while the entire program is running.

(2) It is desirable that the process not be interrupted (such as a page fault) during this reference/update.

For such areas, so-called swap-in/removal is performed, which removes them from the scope of paging, makes all the data resident on the main memory when the data is needed, and sweeps all the data to an external device when it is no longer needed. It is efficient to deal with it using the out method.

Further, as a method of handling data after data is swapped into the main storage device, there is a method called VR in the prior art. This is the idea of matching the logical address of the program/data in the V=R area with the collection address in software, but even with this method, address conversion is required in hardware, and the expansion area If we consider (area of 16 MB or more) as a V-B area, there will be no performance degradation such as page faults, but address translation is also required for the extended area, and even for areas that originally do not require address translation. Don't worry about the increase in hardware due to address translation.

Furthermore, from the software perspective, it is necessary to prepare an address conversion table for use in the extended portion, which results in an increase in main memory capacity and overhead due to its management.

An object of the present invention is to provide an address translation method for solving the above problems.

A feature of the present invention is a means for detecting whether a logical address is within a preset range in an information processing device that uses a virtual memory method that converts a logical address specified by a program into a real address. and a means for selecting either the address after the forward address conversion or the logical address before the address conversion as a containment address according to the error detection result, and the result by the detection means is selected within a preset day. In some cases, even though address conversion is specified, the selection means selects the logical address before the address conversion and uses it as the temporary address.

Another feature is that a means for detecting whether the logical address exceeds a preset value is used as a means for detecting whether the above-mentioned logical address is within a preset range.

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.

FIG. 1 is a diagram showing the relationship between logical addresses and real addresses when the present invention is implemented, and it is assumed that the logical addresses employ a multiple virtual storage system.

Areas ■, ■, ■ on the logical address are common areas of each logical address space, and areas ■, ■, ■■ are areas unique to each logical address space. Also, area (2) is an area exceeding 16 MB, and is the same space as area (2).

By implementing the present invention, allocation of real addresses (which may be considered as addresses on main memory) is performed as follows. The logical address areas ■, ■, ■ are respectively allocated as they are to the real address area 01010, and the logical address areas ■, ■, ■, ■ are divided and allocated in page units (4KB) to the real address area O1■. If the storage device is insufficient, 0 files are stored in the external storage device.The embodiment relates to a method in which an area O with a logical address of 16 MB or more is reassigned to an area (2) at a real address for processing.

FIG. 2 is a diagram showing the address conversion method applied to the present invention, and it is assumed that the logical address register 1 is composed of, for example, s2 bits.

The security circuit vJ2 is a circuit that checks whether the upper 8 bits of the logical address register 1 are zero, and the result is reflected in the code. The address translation parameter y y (TLB) i5 has a copy of a part of the address translation table created by software on the storage device, and is intended to speed up address translation. The comparison circuit 4 compares the logical address in the conversion buffer 5 with a part of the logical address register 1 to check whether the conversion buffer 5 has a necessary real address. The circuit 5 is the output a of the zero check circuit 2.
and the output of the comparator circuit 4, the bit output T specifying address conversion in the register (PSW nigerogram state word) 8 indicating the state of the CPU is input, and depending on the state of the three, the selector signal C1 It outputs a signal d indicating that the desired logical address is not in the conversion buffer. The selector circuit 6 is a circuit that determines whether to select an address after address conversion based on the input signal clc, and its output is input to the real address register 7. Table 1 shows the states of the input and output signals of the circuit 5.

Table 1 Specify T-1 near address conversion mode a=1: Indicates a logical address of 16MB or more showing the b-plot 1 knee-scattering d-1: Indicates that it is not in the TLB Cm00: Do not select 01: Select address after conversion Ru 10: Select the logical address before conversion choose The address conversion method according to the present invention will be explained below.

First, assume that a logical address within 16 MB is set in a logical address register. At this time, the upper 8 bits become zero, so the output signal a of the zero check circuit 2 is 0.
shows. In addition, the output b of the comparator circuit 4 is the register s (PAW
), the select signal C becomes (0%
O) or (0%1)% signal d is 1 or 0. When the select signal C is (0%1) and the signal d is 06, the selection circuit 6 decides to select the address after conversion by the select signal C, and since there is an address corresponding to TLB5, the output of TLB5 is The selected real address is input to the upper bit position of register 7. The lower bits of the logical address are input as they are to the lower bit positions of the real address register 7. When the select signal C is (0, 0) and the signal d is 1, the selection circuit 6 uses the select signal C to select fiTLB.
Neither the output of 5 nor the logical address before conversion is selected. In this case, it is a block diagram of a dynamic address translation mechanism that performs address translation for dynamic address translation. The logical address set in the logical address register 20 and the control register 2
This is performed from the start address of the segment table set to 1 using the segment table 22 and page table 23, which are resident tables in the main memory. The logical address segment, index, and field are used to select one entry in the segment table, and the starting address of the table is indicated by the contents of control register 21. This segment table 22 entry is used as the start address of the page table 25, and is used as the page of logical addresses.

The index field is used to select one entry in the page table 25. This entry includes the upper bits of the real address corresponding to the logical address, and is input into the upper part of the real address register 24. The byte, index, and field of the logical address are stored in the real address register 2 as the lower order of the real address.
It is inputted below 4.

Note that the address conversion using the above-mentioned address conversion mechanism and address conversion buffer is a well-known technique.

Next, consider that a logical address of 16 MB or more is set in the logical address register 2 (see FIG. 2, Table 1). In this case, the signal T of @psw is set to 1 (address conversion is specified).

At this time, the output signal C of the zero check circuit 2 becomes 1, and the value of the output signal C of the circuit 5 becomes (
1% O), the logical address before address conversion is selected as the real address.

That is, based on the signal c(1,0), the selection circuit 6 selects the upper bit of the logical address and inputs it to the upper bit of the real address register 7. The lower bits of the logical address are input to the lower part of the real address register 7.

To summarize the above, when 16MB or less is specified as a logical address, the conventional address conversion method is used, but when 16MB or more is specified as a logical address, address conversion is performed even though address conversion is specified. This is an address conversion method in which a logical address is used as its real address without performing any conversion.

In the above explanation, 16 MB is used as an example of the preset value, but the value may be any number, or it may be a range instead of a value. In the case of B, the method of detecting whether or not the value exceeds a certain value includes a wide range of possibilities, rather than whether it is within a certain range or not.

Figure 4 and below f! 2 shows another embodiment of the present invention.

Table 2 T-1 = Specifies address conversion mode a + = indicates a logical address within the range b-1 indicates a match d-1: indicates not in TLB C 00: not selected Low = after conversion 10: Select the logical address before conversion The difference between FIG. 4 and FIG. This is a circuit 11 that detects whether or not it is within the range. i.e. register 1
0 indicates the range of the logical address.If it is within the range, the logical address is used as the real address without address conversion as in the previous embodiment, and the operation is as described above. It is the same as the example.

According to the present invention, there is no need to perform address translation for addresses greater than a certain value of logical addresses or addresses within a certain range, so that the following effects can be achieved.

Conventional software related to address translation can be used as is without major changes.

Conventional software related to address translation can be used as is without any changes.

In addition, the main memory capacity can be reduced to the extent that an address conversion table for managing logical addresses exceeding a certain value or within a certain range becomes unnecessary.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the relationship between logical addresses and real addresses when the present invention is implemented, FIGS. 2 and 3 are block diagrams of an address translation mechanism according to an embodiment of the present invention, and FIG.
The figure is a schematic diagram of an address translation mechanism according to another embodiment of the present invention. -1...Logical address register 2...Zero check circuit 4...Comparison circuit 5...Circuit 6...
Selection circuit 7...Real address register 8...Register 10
...Register 11 indicating the range of logical addresses...Range detection circuit Figure 1 O 2 Closed

Claims (1)

[Scope of Claims] t An information processing device that adopts a virtual memory method that converts nine logical addresses specified by a program into an inclusive address,
means for detecting whether the logical address is within a preset range; and means for selecting either the address after the serial address translation or the logical address before the address translation as the real address based on the detection result. and when the result by the detection means is within a preset range, the selection means selects the logical address before the serial address conversion and sets it as the real address, even though address conversion is specified. An address translation method featuring: 2. In the address conversion method described in claim 1, the means for detecting whether the logical address is within a preset nine range is to detect whether the logical address exceeds a preset value. An address conversion method that uses means and 411.