JPS589292A - Reading system for read only memory device - Google Patents
Reading system for read only memory deviceInfo
- Publication number
- JPS589292A JPS589292A JP56107764A JP10776481A JPS589292A JP S589292 A JPS589292 A JP S589292A JP 56107764 A JP56107764 A JP 56107764A JP 10776481 A JP10776481 A JP 10776481A JP S589292 A JPS589292 A JP S589292A
- Authority
- JP
- Japan
- Prior art keywords
- defective
- rom
- roms
- read
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 235000012149 noodles Nutrition 0.000 claims 1
- 230000002950 deficient Effects 0.000 description 19
- 230000007547 defect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 101001106432 Homo sapiens Rod outer segment membrane protein 1 Proteins 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- 102100021424 Rod outer segment membrane protein 1 Human genes 0.000 description 1
- 101100524645 Toxoplasma gondii ROM5 gene Proteins 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002716 delivery method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発胸は続出専用記憶装置1(以下ROMと称す)の絞
出し方式に係り同一データを豊込んだ同一種類の3偽以
上の欠陥μOMを使用し、多数決勢の論理処理により出
力値を決定し、各ROMの欠陥を補正11個の完全なR
OMと吟価にするRAM絞出し方式に関する。、
最近漢字を計算機の出力に用いることか多くなってきた
0漢字を記憶するのにはアルファベットとか仮名に比し
字数が多いのでメモリセルが多く必要である。このため
漢字を多数記憶するROM勢は大容量になり例えばウェ
ハより1個しか製作出来ないような大形となる。この為
歩留りが悪く、従来は2つの欠陥ROMを用いその出力
の論理をとることにより出力を決定し相補効果を利用し
て1個の完全なROMとし歩留りを向上していた。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the method of squeezing out the continuous storage device 1 (hereinafter referred to as ROM). The output value is determined by logic processing and the defects of each ROM are corrected.
Regarding OM and the RAM extraction method. In order to memorize the kanji 0, which has recently become more and more often used in computer output, it requires a large number of memory cells to memorize the 0 kanji character, as it has a larger number of characters than the alphabet or kana. For this reason, ROMs that store a large number of kanji characters have a large capacity and are so large that, for example, only one ROM can be manufactured from a wafer. For this reason, the yield is low, and in the past, the output was determined by using two defective ROMs and calculating the logic of their outputs, and the complementary effect was used to create one complete ROM to improve the yield.
第1図は漢字ROM回路の構成原理を示す図で山を出力
している図である。第2図はセル欠陥による誤りを示す
図、第3図は従来例の2個の欠WIlbROMで補正を
行う場合のブロック図である。FIG. 1 is a diagram showing the principle of construction of a kanji ROM circuit, and is a diagram in which mountains are output. FIG. 2 is a diagram showing an error caused by a cell defect, and FIG. 3 is a block diagram when correction is performed using two defective WIlbROMs in the conventional example.
図中1..21,3はROM14はオア(ロ)路、λ1
〜A1・は文字内のドツト位置アドレス、AI、〜A1
1は文字別のアドレス、第1図0の11!は白、′O′
は黒を示す。今第1図囚のROM1に文字別のアドレス
人、、1%−AMを与へ(例へば山)文字内のドツトの
アドレス人1〜人、。を与へると@0に示す如く対応す
る文字に必要なデータが読出される。第1図@0では文
字は10xlO−100個の91 # % Q #で表
わされ合計100個のアドレスで1文字分になる。しか
しROMIのセルのある位置に欠陥があると正しい出力
が得られない。このため欠陥があるROMは不実にして
いた。この歩留り1向上策を以下観測Tる。第2WA(
s)点は10”(黒)であるべき所が11′(白)に←
)点はその逆に誤りをおこした場合を示す・この場合第
3図の如き(ロ)路を用いるとft0M2、ROM3の
出力をオア回路4で論理和をとっているので第211(
Cf)に示す如く一方のROMのセルに欠陥があり%
Q lになっても他方のROMが11#ならば出力は%
1′になるので−)に示す欠陥はなくなる。しかし0)
のような欠陥はなくならない。たが実際の大容fiRO
Mは欠陥セルは10′又は11′のどちらかの出力にな
りやすい傾向に回路上工夫することが出来るので、この
傾向に応じて10′になり易い場合は第3図に示す如く
オア回路4を用い111になり易い場合はアンド回路を
用いる。ことにより欠陥ROMを2個用いて補正して歩
留才りを或程に向上出来る。しかしこの方式ではオア回
路を使用するかアンド回路を使用するかはROMによっ
て足まるのでオア回路を使用すれば第2図(ハ)の如き
欠陥は除去出来ず、アンド回路を使用すれば第2図(ロ
)の如き欠陥は除去出来ず、この場合はこのROMは不
良とするしかなく或程度以上歩雷まりを向上出来ない欠
点がある。1 in the figure. .. 21,3 is ROM14 is or (ro) road, λ1
~A1・ is the dot position address within the character, AI, ~A1
1 is a letter-specific address, 11 of 0 in Figure 1! is white, 'O'
indicates black. Now, give 1%-AM to the ROM1 of the prisoner in Figure 1, 1%-AM, and give the addresses 1 to 1 of the dots within the characters. When , data necessary for the corresponding character is read out as shown by @0. In FIG. 1@0, a character is represented by 10xlO-100 91 # % Q #, making one character with a total of 100 addresses. However, if there is a defect in a certain position of a ROMI cell, correct output cannot be obtained. For this reason, defective ROMs were made unreliable. This yield improvement measure will be observed below. 2nd WA (
s) The point should be 10” (black) but is now 11’ (white)←
) points indicate the case where an error occurs in the opposite case.In this case, if the (b) path as shown in FIG.
As shown in Cf), there is a defect in one of the ROM cells.
Even if Q becomes l, if the other ROM is 11#, the output will be %
1', so the defect shown in -) disappears. But 0)
Such defects will not go away. However, the actual large capacity fiRO
Since M can be devised in the circuit so that defective cells tend to output either 10' or 11', if M tends to output 10' according to this tendency, the OR circuit 4 is used as shown in Figure 3. If the result is likely to be 111, an AND circuit is used. By doing so, it is possible to correct the defective ROM by using two defective ROMs and improve the yield to some extent. However, in this method, whether to use an OR circuit or an AND circuit depends on the ROM, so if an OR circuit is used, the defects as shown in Figure 2 (c) cannot be removed, and if an AND circuit is used, the second Defects such as those shown in Figure (b) cannot be removed, and in this case, the ROM has no choice but to be considered defective, and has the disadvantage that it is not possible to improve the processing speed beyond a certain degree.
本発明の目的は上記の欠点をなくするために3個以上の
欠陥ROMを用いることによりROM内の欠陥セルを殆
んど完全に補正し1個の完全なROMとして使用出来る
歩留のよいR0M[出し方式の提供にある。The purpose of the present invention is to eliminate the above-mentioned drawbacks by using three or more defective ROMs to almost completely correct the defective cells in the ROM and to provide a high-yield ROM that can be used as one complete ROM. [Providing a delivery method]
本発明は上記の目的を達成するために同一内容のデータ
を記憶した同一種類の3個以上の続出専用記憶装置に、
同一読出しセル指定のアドレスを与え、各続出専用記憶
装置よりの出力情報を比較し、違いがあれば、どちらか
にする判断基準をもうけ、出力値を決定し、その値を読
出専用記憶装置の読出し情報とすることを特徴とする読
出専用記憶装置読出し方式である。In order to achieve the above object, the present invention provides three or more successive storage devices of the same type storing data of the same content.
Give the same read cell designation address, compare the output information from each successive read-only storage device, and if there is a difference, create a criterion for selecting one or the other, determine the output value, and transfer that value to the read-only storage device. This is a read-only storage device read method characterized by using read information.
以下本発明の1実施例につき図に従って説明する。第4
図は本発明の実施例の欠陥ROMを3個用いて補正を行
う場合のブロック図である。An embodiment of the present invention will be described below with reference to the drawings. Fourth
The figure is a block diagram when correction is performed using three defective ROMs according to an embodiment of the present invention.
図中第1図と同一機能のものは同一記号で示もs、2g
、7はROM、8は多数決回路である。Items with the same functions as those in Figure 1 are indicated by the same symbols, s, 2g.
, 7 is a ROM, and 8 is a majority circuit.
)t+OMs、、6e、7は同一内容のデータを配憶し
た同一種類のROMでアドレスの内容も同一である。)t+OMs, , 6e, and 7 are the same type of ROMs that store the same data and have the same address content.
従ってROM5..61,7に文字別アドレスAll
S−AMを与へ文字内のドツトのアドレスA、〜A、。Therefore, ROM5. .. All character-specific addresses in 61 and 7
Given S-AM, the address of the dot in the character A, ~A,.
を与えると同じ内容の出力JI又は11′が出力され多
数決回路8にて多数決をとり1個のROMの出力として
出力される。令弟2図fOに)に示す如き欠陥がありて
も10′又は11#の多い方を多数決回路8にて選択す
るので欠陥は補正される。従ってこの場合は2個のRO
Mが同じ位置に欠陥セルをもたなければ第2図句に)い
づれのタイプの欠陥も除去出来る。故にこの場合には欠
陥セルが10#用いづれかに固定されやすいような回路
上の工夫も必要なく、又2個のROMが同じ位置に欠陥
セルを持つことはまずないので欠陥のあるROMを3個
用いることで完全なROM1個として使用出米歩留まり
を向上出来る。本実施例は3sの欠陥ROMを使用する
ことで観、明したがこれは4個以上でもよく又多数決回
路は例えば4個の欠陥ROMを使用し1個以下の違いを
補正するような歩留りを考慮した判断方法をとってもよ
い。When , the output JI or 11' having the same content is output, and the majority decision is taken by the majority circuit 8, and the result is output as the output of one ROM. Even if there is a defect as shown in FIG. Therefore, in this case, two ROs
If M does not have a defective cell at the same location, either type of defect can be removed (see Figure 2). Therefore, in this case, there is no need to create a circuit in which the defective cells are easily fixed using 10#, and since two ROMs rarely have defective cells in the same position, the defective ROM is By using two complete ROMs, the production yield can be improved. This embodiment was explained by using 3s of defective ROMs, but the number of defective ROMs may be four or more, and the majority circuit uses, for example, four defective ROMs to correct for a difference of one or less. You may use a method of judgment that takes this into account.
以上詳細に説明した如く本発明によれば3個以上の欠陥
ROMを用いて1個の完全なR,OMとして使用出来る
ので大容量ROMの歩留を向上出来る効果がある。As described in detail above, according to the present invention, three or more defective ROMs can be used as one complete R, OM, thereby improving the yield of large capacity ROMs.
第1図は漢字ROM回路の構成原理を示す図で山を出力
している図、第2図はセル欠陥による誤りを示す図、第
3図は従来例の2個の欠陥ROMで補正を行う場合のブ
ロック図、館4図は本発明の実施例の欠−ROMを3個
用いて補正を行う場合のブロック図である。図中1す2
□3..5h、 6.、 ’1はROM、4はオア回路
、8は多数決回路、鳥〜Al11は文字内のドツト位置
アドレス、A□〜Axは文字別アドレス、第1図0の1
1#は白、′0#は黒を示す。
代理人1−理士 松 −宏四−ン憬
第1図
(Bン
11//lθ//ll
1llllθ///1
1111/llllIFigure 1 is a diagram showing the configuration principle of the Kanji ROM circuit, which outputs mountains, Figure 2 is a diagram showing errors due to cell defects, and Figure 3 is correction using two defective ROMs in the conventional example. Figure 4 is a block diagram of the case where correction is performed using three missing ROMs according to the embodiment of the present invention. 1 and 2 in the diagram
□3. .. 5h, 6. , '1 is the ROM, 4 is the OR circuit, 8 is the majority circuit, Bird~Al11 is the dot position address within the character, A□~Ax is the address for each character, 1 in Figure 1 0
1# indicates white and '0# indicates black. Agent 1 - Physician Matsu - Hiroshi-Nyun Figure 1 (Bn11//lθ//ll 1llllθ///1 1111/lllllI
Claims (1)
+専用記憶懺置装、同−妖出しセル指定のアドレスを与
え、各訳出専用記憶妓歓よりの出力情報を比較し、違い
があれば、どちらかにする判断基準をもうけ、出力値を
決定し、その値を欽出専用記憶装置の読出し情報とする
ことを特徴とする続出専用記憶装置iIL続出し方式。3 or more *a of the same noodles that memorized the same self-answer data
+ Dedicated memory device, same - Give the designated address of the translation cell, compare the output information from each translation dedicated memory device, and if there is a difference, create a judgment criterion to select one or the other, and determine the output value. and the value thereof is used as read information of the successive-only storage device iIL.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56107764A JPS589292A (en) | 1981-07-10 | 1981-07-10 | Reading system for read only memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56107764A JPS589292A (en) | 1981-07-10 | 1981-07-10 | Reading system for read only memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS589292A true JPS589292A (en) | 1983-01-19 |
Family
ID=14467397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56107764A Pending JPS589292A (en) | 1981-07-10 | 1981-07-10 | Reading system for read only memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS589292A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60173800A (en) * | 1983-10-28 | 1985-09-07 | シ−ク テクノロジ− インコ−ポレ−テツド | Faul allowable memory array |
JPH0730435A (en) * | 1993-07-14 | 1995-01-31 | Nec Corp | Error correcting circuit |
-
1981
- 1981-07-10 JP JP56107764A patent/JPS589292A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60173800A (en) * | 1983-10-28 | 1985-09-07 | シ−ク テクノロジ− インコ−ポレ−テツド | Faul allowable memory array |
JPH0458680B2 (en) * | 1983-10-28 | 1992-09-18 | Shiiku Tekunorojii Inc | |
JPH0730435A (en) * | 1993-07-14 | 1995-01-31 | Nec Corp | Error correcting circuit |
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