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JPS5892152A - Control circuit for automatic frequency characteristics - Google Patents

Control circuit for automatic frequency characteristics

Info

Publication number
JPS5892152A
JPS5892152A JP19008381A JP19008381A JPS5892152A JP S5892152 A JPS5892152 A JP S5892152A JP 19008381 A JP19008381 A JP 19008381A JP 19008381 A JP19008381 A JP 19008381A JP S5892152 A JPS5892152 A JP S5892152A
Authority
JP
Japan
Prior art keywords
circuit
control circuit
differential amplifier
amplifier circuit
frequency characteristics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19008381A
Other languages
Japanese (ja)
Inventor
Minoru Sakai
坂井 実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19008381A priority Critical patent/JPS5892152A/en
Publication of JPS5892152A publication Critical patent/JPS5892152A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/04Control of transmission; Equalising
    • H04B3/06Control of transmission; Equalising by the transmitted signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は文字図形情報を受信する端末の後胴回路におい
て、センターより送られる信号(以下下り信号といり)
のW波数特性の傾きを自動的に制御llフラットにする
回路に関する本のである。
[Detailed Description of the Invention] The present invention provides a signal (hereinafter referred to as a downlink signal) sent from the center in the rear body circuit of a terminal that receives character and graphic information.
This is a book about a circuit that automatically controls and flattens the slope of the W wavenumber characteristic of .

従来の作−回路には、手動切替スイッチにおいて、あら
かじめ決められた周波数特性に設定出来る振輻岬什回路
は付加されているが、これではステップが大きいため下
り信号のm*数特性の傾きはかなり残っており%また、
電話口114端末をセンターと接続すふ都膨変わるとと
があり、これ本領きを悪化させ石原因1!−なり、麹g
seのアイ開口を小さくしてビット誤り率を悪くすると
いう欠点が車った。
In the conventional operation circuit, a vibration cape circuit that can set a predetermined frequency characteristic with a manual changeover switch is added, but since the step is large, the slope of the m* number characteristic of the downlink signal is There is quite a bit left and %Also,
Connecting the telephone port 114 terminal to the center causes a change in the volume, which worsens the main function and causes problems! -Naru, koji g
The drawback is that it reduces the eye opening of SE and worsens the bit error rate.

本発明の目−は、上記した従来技術の欠点を無<15、
下り信号の周波数特性の傾きを自動的に制御し、フラッ
トにする復−回路を捷供することKある。
The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art by eliminating <15.
It is possible to provide a return circuit that automatically controls and flattens the slope of the frequency characteristic of the downlink signal.

本発明社自動利得制御後の下り信号をl!l皺BPF(
高琥帯綾フィルタ)、低炉BPF(低竣帯竣フィルタ)
てそれぞれの周波数成分に分解し、それぞれ検波整波し
て、その差を差動増幅回路で増幅し、千の出力電圧てダ
イオード等の等価抵抗を変化させ、これによって自動利
得制御回路の前にもつけた周波数制御可能な増幅回路の
周波#j特性を制御して、常に下り信号の周波数特性を
フラットにするように横e1.たことを特徴とする本の
である。
The downlink signal after the automatic gain control of the present inventor is l! l wrinkle BPF (
Takahan Obi-Aya Filter), Low Furnace BPF (Low-furnace Obi-Aya Filter)
They are separated into their respective frequency components, each detected and rectified, and the difference is amplified by a differential amplifier circuit, and the output voltage is changed by a diode or other equivalent resistance. The horizontal e1. This is a book that is characterized by

月下1本発明を図面を用りて説明する。!1図に本発明
の自動周波数特性制御回路の一実施例を、第2図に増幅
回路30II波数特性を、第3図に各条件における自動
1ili1波数特性制御回路の制御動作を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained with reference to the drawings. ! FIG. 1 shows an embodiment of the automatic frequency characteristic control circuit of the present invention, FIG. 2 shows the wave number characteristics of the amplifier circuit 30II, and FIG. 3 shows the control operation of the automatic 1ili1 wave number characteristic control circuit under various conditions.

@1図におりで、電話回線を使用してセンターから送ら
れてきた下り信号はハイブリッドトランス、下り信号H
PF(高域フィルタ)、振幅婢化器郷を通して本発明に
よる自動周波数特性制御回路1[伝送され、次段の自動
利得制御回路2に伝送されふ。
@Figure 1 shows that the downlink signal sent from the center using the telephone line is a hybrid transformer, and the downlink signal H
The signal is transmitted to the automatic frequency characteristic control circuit 1 according to the present invention through a PF (high-pass filter) and an amplitude modifier, and is then transmitted to the automatic gain control circuit 2 at the next stage.

自動利得制御回路2の出力信号の一部は高域BPF4 
(たとえげ2200±400Hg程度とスル)と(l[
’BPF6(たとえば1000±400Hg程度とする
)に伝送される。高jdBPF4を通った信号は検波・
整流回路5で直流に変換され、差動増幅回路8のO端子
に1低緘B P 1!l 6を通った信号は検波整流回
路フで直流に変換さn1差動増幅回路8の○端子に供給
される。この差動増幅回路8によってとの■O端子の差
電圧が増幅され、制御回路9の中のダイオード9aのア
ノードに供給される。このダイオード9aの等価抵抗を
Rとすると、このRは差動増幅回路8の出力電圧が大き
くなると小さくなり(0Ωに近づく)、逆に小さくなる
と大きくなる(ooΩに近づく)、このRの変什により
第2図の特性10,11.12の様なWpUtIt数特
性を増幅特性3に持たせることにより、自動&i1波数
特性制御が可能となる。第2図の特性’10,11.1
2はダイオード9aの等価抵抗がR,、oo、 Oの場
合を示してhる。通常はR# R1の状111に設定す
ることにより増幅回路3の119数特性はフラットにな
っている。
A part of the output signal of the automatic gain control circuit 2 is a high-frequency BPF 4.
(For example, about 2200±400Hg) and (l[
' It is transmitted to BPF6 (for example, about 1000±400Hg). The signal passing through the high jdBPF4 is detected and
It is converted into direct current by the rectifier circuit 5, and is connected to the O terminal of the differential amplifier circuit 8. The signal that has passed through l6 is converted into direct current by the detection rectifier circuit F and is supplied to the O terminal of the n1 differential amplifier circuit 8. This differential amplifier circuit 8 amplifies the voltage difference between the terminals 1 and 1, and supplies the amplified voltage to the anode of a diode 9a in the control circuit 9. Assuming that the equivalent resistance of this diode 9a is R, this R decreases as the output voltage of the differential amplifier circuit 8 increases (approaches 0Ω), and conversely increases as the output voltage decreases (approaches ooΩ). By providing the amplification characteristic 3 with WpUtIt number characteristics such as characteristics 10, 11, and 12 in FIG. 2, automatic &i1 wave number characteristic control becomes possible. Characteristics in Figure 2 '10, 11.1
2 shows the case where the equivalent resistance of the diode 9a is R, oo, O. Normally, by setting R# R1 to 111, the 119 characteristic of the amplifier circuit 3 becomes flat.

さて、ことて何らかの原因で自動利得制御回路2の下り
信号出力が第3図(a)の様に低域1i1ff数で低レ
ベルに、高域周波数で高レベルになったとすると、高域
BPF4.検波検波回路5を通って差動増幅回路8の■
端子の電圧と、低域BPF6.検波整流回路フを通って
差動増幅回路8の○端子の差電圧は、通常時より大きく
なるため差動増幅回路8の出力電圧が通電°時より大き
くなり、RがOΩに近づく、これにより%l/ES図(
1))のごとく増幅回路30周波数特性は、高域で低利
得、低綾で高利得となるため、増幅回路3の出力及び自
動利得制御回路2の出力の周波数特性は第3図(e)の
様にはtYフラットになる。第3図(d)(151(f
lに自動利得制御回路2の下り信号出力がフラットの時
、第3図(g)(h)(1)K、何らかの原因で自動利
得制御回路2の下り信号出力が低域j1!波数で高レベ
ルに高塚周波数で低レベルになった時の制御動作を示し
ている。
Now, if for some reason the downstream signal output of the automatic gain control circuit 2 becomes a low level at the low frequency 1i1ff number and a high level at the high frequency as shown in FIG. 3(a), then the high frequency BPF4. ■ of the differential amplifier circuit 8 through the detection circuit 5
Terminal voltage and low range BPF6. The voltage difference between the terminals of the differential amplifier circuit 8 after passing through the detection rectifier circuit becomes larger than normal, so the output voltage of the differential amplifier circuit 8 becomes larger than when the current is energized, and R approaches OΩ. %l/ES diagram (
As shown in 1)), the frequency characteristics of the amplifier circuit 30 are low gain in the high range and high gain in the low range, so the frequency characteristics of the output of the amplifier circuit 3 and the output of the automatic gain control circuit 2 are as shown in Fig. 3(e). The result is tY flat. Figure 3(d) (151(f)
When the downstream signal output of the automatic gain control circuit 2 is flat at l, the downstream signal output of the automatic gain control circuit 2 is in the low range j1! for some reason. It shows the control operation when the wave number becomes high level and the Takatsuka frequency becomes low level.

この様に、下り信号の周波数特性が高低どちら側に傾り
ていて本、自動的にフラグ)Kする自動周波数特性制御
が可能となる。
In this way, it is possible to perform automatic frequency characteristic control that automatically flags whether the frequency characteristic of the downlink signal is inclined to the high or low side.

本発明により、電話回線として使用する電送ケーブルの
種類、あるいは端末内復調回路の振幅醇化片寄プ婢によ
って発生する周波数特性の仙きが無くなるため、復訓時
のアイ開口が大きくなり、ビット誤り率が改善される。
The present invention eliminates fluctuations in frequency characteristics caused by the type of transmission cable used as a telephone line or the amplitude imbalance of the demodulation circuit in the terminal, so the eye opening during decoding becomes larger and the bit error rate increases. is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による自動周波数特性制御回路の一実施
例を示す回路図、第2図は第1図の中の増幅回路のji
!1tIJt数特性図、第3図は各条件における自動周
波数特性制御回路の制御動作を示す周波数蒔性図である
。 1・・・自動周波#!i特性制御回路 番00.高域BPF 5・・・低績BPF 9・・・制御回路 代理人 弁理士 渡 辺 文 雄 才 try l −−−−−−−−−−一−−−−−−−−−−−−−−
−−−−−−J牙 2 図
FIG. 1 is a circuit diagram showing an embodiment of the automatic frequency characteristic control circuit according to the present invention, and FIG.
! 1tIJt number characteristic diagram. FIG. 3 is a frequency distribution diagram showing the control operation of the automatic frequency characteristic control circuit under various conditions. 1...Auto frequency #! i-characteristic control circuit number 00. High BPF 5...Low BPF 9...Control circuit agent Patent attorney Fumi Watanabe Yusai try l −−−−−−−−−−1−−−−−−−−−−−− ---
−−−−−−J Fang 2 Figure

Claims (1)

【特許請求の範囲】[Claims] 電話回線を使用して文字図形情報を受信すふ端末の腹−
回路において、センターから伝送される信号の高域成分
を抜きとる高鞍帯域フィルタと低謔成分を抜角とる低炉
帯竣フィルタと、該2個の帯−フィルタ出力をそれぞれ
検波、整流する2個の#波PWF回路と、v12個の検
波、整流出力の差を増幅する差動増幅回路と、1差動増
幅回路の出力電圧によって等価抵抗を変える制御回路と
、該制御回路によってセンターから伝送される信号の周
波数特性を制御する増W回路で楢放されたことを特徴と
する自動8波数特性制御回路。
The back of the terminal that receives text and graphic information using the telephone line.
The circuit includes a high band filter that extracts high frequency components of the signal transmitted from the center, a low band filter that extracts low frequency components, and 2 that detects and rectifies the outputs of the two band filters, respectively. A # wave PWF circuit, a differential amplifier circuit that amplifies the difference between v12 detection and rectification outputs, a control circuit that changes the equivalent resistance depending on the output voltage of the 1 differential amplifier circuit, and transmission from the center by the control circuit. An automatic 8-wavenumber characteristic control circuit characterized in that it is expanded by a W increase circuit that controls the frequency characteristics of a signal.
JP19008381A 1981-11-27 1981-11-27 Control circuit for automatic frequency characteristics Pending JPS5892152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19008381A JPS5892152A (en) 1981-11-27 1981-11-27 Control circuit for automatic frequency characteristics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19008381A JPS5892152A (en) 1981-11-27 1981-11-27 Control circuit for automatic frequency characteristics

Publications (1)

Publication Number Publication Date
JPS5892152A true JPS5892152A (en) 1983-06-01

Family

ID=16252078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19008381A Pending JPS5892152A (en) 1981-11-27 1981-11-27 Control circuit for automatic frequency characteristics

Country Status (1)

Country Link
JP (1) JPS5892152A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01129622A (en) * 1987-11-16 1989-05-22 Fuji Xerox Co Ltd Facsimile equipment
JPH01157629A (en) * 1987-12-15 1989-06-20 Fujitsu Ltd Phase reversal detection method
JP2007195204A (en) * 2007-02-09 2007-08-02 Ricoh Co Ltd Modulation/demodulation apparatus and demodulation method thereof, and program thereof and recording medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55102935A (en) * 1979-01-31 1980-08-06 Nec Corp System and device for amplitude equalization

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55102935A (en) * 1979-01-31 1980-08-06 Nec Corp System and device for amplitude equalization

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01129622A (en) * 1987-11-16 1989-05-22 Fuji Xerox Co Ltd Facsimile equipment
JPH01157629A (en) * 1987-12-15 1989-06-20 Fujitsu Ltd Phase reversal detection method
JP2007195204A (en) * 2007-02-09 2007-08-02 Ricoh Co Ltd Modulation/demodulation apparatus and demodulation method thereof, and program thereof and recording medium
JP4545161B2 (en) * 2007-02-09 2010-09-15 株式会社リコー Modulator / demodulator, demodulation method thereof, program and recording medium thereof

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