JPS588616B2 - Charge storage charge/discharge circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a charging/discharging circuit for a charge storage body.

A charge storage body with extremely low leakage current can utilize its integral effect in a timer or the like.

When using a charge accumulator for such purposes, a mechanism for quickly setting the initial charging current and a constant current charging/discharging mechanism are required.
The main condition is that when these mechanisms are connected to a charge storage, their leakage current does not increase.

The use of mechanical switches in these mechanisms makes the requirements relatively easy to meet, but makes electrical control of timer operation cumbersome.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a semiconductor control circuit that can maintain performance equal to or better than a mechanical switch over a wide temperature range and is easy to control. There is a particular thing.

According to the present invention, a composite complementary circuit is provided in which the electrical neutral points of an arbitrary complementary circuit and other complementary circuits in which the order of complementary elements in the complementary circuit is switched are connected to each other, and this is used as an output terminal. When the circuit is used to control a charge storage, a complementary circuit including the charge storage in a control input circuit is used to set the initial charge amount of the charge storage, and a complementary circuit including the charge storage in the control input circuit is used to set the initial charge amount of the charge storage. A charge accumulator charging/discharging circuit is obtained, which is characterized in that a complementary circuit that does not include a charge accumulator is used for charging and discharging a charge accumulator for the purpose of time-limiting operation.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The drawing is a circuit diagram showing an embodiment of the charge storage charging and discharging circuit according to the present invention.
The first electrode 11 of 0 is connected to the midpoint 23 of the composite complementary amplifier circuit 20, and the second electrode 12 is connected to the GND (ground) potential.

The third electrode 13 is provided for detecting the amount of charge, and generates a voltage equal to that of the first electrode 11, but its internal impedance is extremely large.

The composite complementary circuit 20 includes a complementary stage 21 for setting an initial charge amount consisting of transistors Q1 and Q2, and transistors Q3 and Q.
The constant current charging/discharging complementary stage 22 consists of four transistors, and the midpoints of each of them, that is, the connection point of the source electrodes of the transistors Q1 and Q2 and the connection point of the drain electrodes of the transistors Q3 and Q4, are commonly connected. A neutral point 23 is formed.

The neutral point 23 becomes the output terminal of the composite complementary circuit 20.

The drain of the transistor Qt and the source of the transistor Q3 are respectively connected to a terminal 24 to which the power source E1 is coupled, while the drain of the transistor Q2 and the source of the transistor Q
4 sources are respectively connected to terminals 25 to which a power source E2 is coupled.

The neutral terminal is a transistor Q between terminals 24 and 25.
variable resistor VR1 coupled to the gate of transistor Q3 and variable resistor V whose neutral terminal is coupled to the gate of transistor Q4.
R2 are connected in series.

Composite complementary amplifier circuit 20 is manufactured using integrated circuit technology, for example, and the electrical and thermal characteristics of N-channel FET transistors Q1 and Q4 or P-channel FET transistors Q2 and Q3 can be well matched. .

Complementary stage 21 is a circuit that includes charge storage 10 in its control input circuit, while complementary stage 22 is a circuit that does not include charge storage 10 in its control input circuit.

Since the current flowing through the circuit connecting the first electrode 11 and the neutral point 23 when there is no control signal at the gate of each MOS transistor becomes a leakage current as an external circuit to the charge storage body 10, in this case, It is desirable that the leakage current I6=OnA.

Today, drain leakage current (transistors Q1, Q2
The drain leakage currents of Q3 and Q4 are respectively idss1 and i
dss2, idss3, idss4) are ids
An integrated circuit element such that s1=idss4 idss3=idss2 ∴idss1+idss3=idss4+idss2 can be easily realized, and the neutral point 23
Since the potential of FE can be made equal to the GND potential, the first electrode 11 and the second electrode 12 have the same potential.
Even if there is a leakage current in the T transistor itself, it does not become a load on the charge storage element 10.

As a control element for the charge storage element 10, it is natural to use an enhancement FET transistor whose leakage current is smaller than that of a bipolar element.
The feature of the present invention is that in order to balance the characteristics, all four FET transistors are not used for charging and discharging the charge storage element 10, but two are made into a set, and the usage is limited for each set. It is in.

It goes without saying that not only enhancement type transistors but also depletion mode transistors can be used by appropriately applying a bias voltage.

Next, to explain the operation, transistors Q1 and Q2
Each source terminal is connected to GND via the neutral point 23 and the charge storage element 10.

Therefore, in the first state, the charge storage element 10 can be considered as a battery with zero charge, so the transistors Q1 and Q
Each source terminal of the charge storage element 10 reaches GND through a slight internal resistance of the charge storage element 10.

When a switching voltage sufficiently larger than the threshold voltage is applied between the gate and source of transistor Q1, transistor Q1
turns "ON" and rapidly charges the charge storage element 10.

That is, the charge storage body 10 is charged by the power source E1 through the drain, source, and neutral point 23 of the "ON" transistor Q1.

Therefore, the potential of the first electrode 11 with respect to GND increases in proportion to the amount of charge (product of charging current and charging time).

This potential is negatively fed back to the transistor Q1 and acts in a direction to decrease the drain current of the transistor Q1, so that the drain current of the transistor Q1 decreases with time.

However, if the potential applied between the gate of Q1 and GND can be made sufficiently larger than the potential generated by the charge storage element 10, this effect can be ignored, and in that case charging (on the order of several milliamps) will proceed rapidly. .

In the case of overcharging, a switching voltage with a polarity opposite to that of the gate of the transistor Q1 is applied between the gate of the transistor Q2 and GND to turn the transistor Q2 "ON" and discharge the charge in the charge storage body 10.

Through these operations, the initial charge amount can be quickly set.

The timer action is produced by changing the amount of charge on the charge storage element 10 using a constant current source.

As already explained, the transistor Q1 or Q2 cannot be expected to have constant current property due to the negative feedback effect caused by charging the charge storage body 10, so each source is directly connected to the positive or negative power supply line. FET transistors Q3 and Q4 are used as a constant current charging/discharging complementary stage, and the gate potential of each is finely adjusted by variable resistors VR1 and VR2 to set a constant current value.

It is easy to make a timer for several hours with this current value on the order of microamperes.

For example, the drain current of the transistor Q4 is set to a constant value, and the transistors Q1, Q2, and Q3 are turned "OFF" to discharge the charges in the charge storage element 10.

In this case, the current is discharged at a constant current through the midpoint terminal 23, the internal resistance of the transistor Q4 set by the variable resistor VR2, and the power source E2.

It goes without saying that if the time when the amount of charge becomes zero, that is, the potential of the third electrode 13 becomes 0V, is detected, this detected time becomes, for example, the time of a timer.

When it is desired to change the operating time, it is common to adjust the initial charge amount.

As a long-time timer, the drain current of transistor Q3 or Q4 is required to be very small and to have constant current characteristics, but in the present invention, an FET transistor having constant current characteristics is used, and its constant current characteristics As a result, fluctuations in power supply voltage are absorbed, and changes in leakage current due to temperature changes are canceled out in terms of the circuit, so that the required accuracy in charging and discharging current can be maintained.

As in this embodiment, the complementary stage 21 including the charge accumulator 10 is used in the control input circuit to set the initial charge amount in which the charging/discharging current is large and accuracy is not required in the composite complementary control circuit. For time-limited applications where stability is required, a complementary stage 22 in which the connection order of complementary elements is reversed and does not include the charge accumulator 10 in the control input circuit is used to achieve a constant current that cannot be achieved with a mechanical switch. characteristics and electrical remote control can be easily obtained.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an illustrative example, and it goes without saying that the present invention is not limited only to the embodiment shown here.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of a charge storage charge/discharge circuit according to the present invention. Q1-Q4...Transistor, E1, E2...
...Power supply, 10...Charge accumulator, 11-1
3... Electrode, 20... Composite complementary amplifier circuit, 21... Complementary stage for initial charge amount setting, 22...
... Constant current charging/discharging complementary stage, 23, 24...
・Terminal.

Claims (1)

[Claims] 1 A first complementary circuit formed by connecting a first transistor of one conductivity type and a second transistor of the other conductivity type in series, and a third transistor of one conductivity type and a fourth transistor of the other conductivity type connected in series. a second complementary circuit in parallel, a series connection point of the first and second transistors and a series connection point of the third and fourth transistors, and a charge storage body is connected to the connection point. , wherein the first complementary circuit is used for setting the initial charge amount of the charge storage body, and the second complementary circuit is used for charging and discharging the charge storage body with a constant current. body charge/discharge circuit