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JPS5885204U - Sequence control device - Google Patents

Sequence control device

Info

Publication number
JPS5885204U
JPS5885204U JP14870482U JP14870482U JPS5885204U JP S5885204 U JPS5885204 U JP S5885204U JP 14870482 U JP14870482 U JP 14870482U JP 14870482 U JP14870482 U JP 14870482U JP S5885204 U JPS5885204 U JP S5885204U
Authority
JP
Japan
Prior art keywords
main body
control device
sequence control
memory unit
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14870482U
Other languages
Japanese (ja)
Other versions
JPS6239441Y2 (en
Inventor
小野木　俊郎
与田　健一
昌彦 北村
Original Assignee
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電工株式会社 filed Critical 松下電工株式会社
Priority to JP14870482U priority Critical patent/JPS5885204U/en
Publication of JPS5885204U publication Critical patent/JPS5885204U/en
Application granted granted Critical
Publication of JPS6239441Y2 publication Critical patent/JPS6239441Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１蓉乃至第３図は本考案の実施例を示し、第１図は分
解斜視図、第２図は組立状態の正面図、第３図は回路ブ
ロック図である。・ １：入力端子、２：入力回路、３：コネクタ、３′　：
コネクタ、４：出力回路、５：出力端子、６：電源端子
、７：電源解路、１０：メモリユニット、　、１１：開
口部、１１′　：開口部、１２　：Ｅ−Ｐ−ＲＯＭ。 １３：つば、１４：ケース、Ａ：本体、Ｄ＝制御ユニッ
ト。1 to 3 show an embodiment of the present invention, in which FIG. 1 is an exploded perspective view, FIG. 2 is a front view of an assembled state, and FIG. 3 is a circuit block diagram.・ 1: Input terminal, 2: Input circuit, 3: Connector, 3':
Connector, 4: Output circuit, 5: Output terminal, 6: Power supply terminal, 7: Power supply disconnection, 10: Memory unit, , 11: Opening, 11': Opening, 12: E-P-ROM. 13: Brim, 14: Case, A: Main body, D = Control unit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号によりメモリのプログラムに従いシーケンス出
力が出力されるシーケンス制御装置において、略矩形の
制御ユニットの本体内に入力回路、出力回路等からなる
制御回路を収納し、プログラムを記憶させであるＲＯＭ
を本体に対して着脱自在に装着かつ接続するメモリユニ
ットのケース内に収納し、本体には入力端子、出力端子
、電源端子を備えて本体両側に入力端子と出力端子とを
互いに対設し、これら端子のない本体の部位にはメモリ
ユニット接続用の雄側コネクタを設け、メモリユニット
のケースの片側に開口部を形成して該開口部には前記雄
側コネクタに対応するケース内に設けた雌側コネクタを
臨ませるとともにＲＯＭを臨ませて成るシーケンス制御
装置。In a sequence control device that outputs a sequence output according to a program in a memory based on an input signal, a control circuit consisting of an input circuit, an output circuit, etc. is housed in the main body of a substantially rectangular control unit, and a ROM is used to store the program.
is housed in a case of a memory unit that is detachably attached to and connected to the main body, and the main body is provided with an input terminal, an output terminal, and a power terminal, and the input terminal and output terminal are arranged opposite to each other on both sides of the main body. A male connector for connecting the memory unit is provided in a portion of the main body that does not have these terminals, an opening is formed on one side of the case of the memory unit, and the opening is provided in the case corresponding to the male connector. A sequence control device that includes a female connector and a ROM.
JP14870482U 1982-09-30 1982-09-30 Sequence control device Granted JPS5885204U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14870482U JPS5885204U (en) 1982-09-30 1982-09-30 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14870482U JPS5885204U (en) 1982-09-30 1982-09-30 Sequence control device

Publications (2)

Publication Number Publication Date
JPS5885204U true JPS5885204U (en) 1983-06-09
JPS6239441Y2 JPS6239441Y2 (en) 1987-10-08

Family

ID=29941512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14870482U Granted JPS5885204U (en) 1982-09-30 1982-09-30 Sequence control device

Country Status (1)

Country Link
JP (1) JPS5885204U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570702U (en) * 1978-11-09 1980-05-15
JPS5588102A (en) * 1978-12-27 1980-07-03 Omron Tateisi Electronics Co Sequence programmer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570702U (en) * 1978-11-09 1980-05-15
JPS5588102A (en) * 1978-12-27 1980-07-03 Omron Tateisi Electronics Co Sequence programmer

Also Published As

Publication number Publication date
JPS6239441Y2 (en) 1987-10-08

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