JPS5884530A - Analog-to-digital converting method and device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention calculates an analog signal applied to the input of an analog-to-digital (A-D) converter with respect to a low level limit and a high level limit to which the converter responds. The present invention relates to an A-D conversion method and a conversion device used in this process. The amplitude of the analog signal measured by the maximum and minimum values of the signal handled here may vary over time. The present invention is particularly useful for receiving the amplitude of an analog signal, or its maximum, large and minimum levels (referred to herein as average DC level or simply DC level), or both. variable gain amplifier or D
It is particularly useful in schemes for adjusting with respect to the limits of the input of an A-D converter by controlling the C-level control circuit (or both).

The analog-to-digital converter produces, over the observed time length of the analog signal, a digital word having a value representing the amplitude of the samples of the input analog signal sampled over that time length. Ideally, the amplitude and average DC level range of the analog signal does not change over time, and the transducer also ensures that the sampled amplitude of the expected analog signal is at a low level in the input range of the transducer. It is designed to be within (matching) the low and high level limits, and for example to center the range of the low and high level limits at the expected average DC level of the analog signal. Under these conditions, the transducer generates a digital word of value (e.g., all Ol or all l) representing samples of the analog signal that lie below or above the limit value of the input range of the transducer. do not have to.

In order to match the analog signal to one of the limits of the signal range to which the A/D converter responds, the amplitude of the analog signal is adjusted to a value smaller than the ideal method.
Corkhill (Oorkhill) dated March 30, '/6
) et al., U.S. Pat. No. 3.94'/, 806
It is stated in the specification of the issue. This patent specification describes an automatic gain control circuit ( A converter with an AGC circuit) is shown. This device matches the maximum amplitude of the analog signal to the upper limit of the converter's input range, but when the consistently occurring maximum of the analog signal's amplitude falls below the lower limit of the converter's input, It is not possible to increase the amplitude. Also, the device shown in the above patent specification.

The AGC circuit is responsive to each maximum digital word taken from the analog signal whose amplitude is equal to or exceeds the upper limit of the input range of the converter; Respond to samples of isolated analog signals. Furthermore, this device does not include means for controlling the average DC level of the analog signal supplied to the A-D converter.

As discussed here, the amplitude of the average analog signal is A-
If the input limits of the D-converter are not matched, the value of the digital word produced by the A-D converter can drop to a minimum value (i.e. all O) and also to a maximum value (i.e. all I). It can increase. It is an object of the invention to calculate the value of an analog signal by determining the value of the digital word produced by the A-to-D converter in relation to the known lower and upper limits of the range of the signal to which the A-to-D converter responds. The purpose is to calculate the amplitude. Such calculations then allow adjustments to be made to the analog signal amplitude or average DC level, or both. -More specifically, the invention relates to a method for determining the amplitude and/or reference level occurring within a predetermined length of time of an analog signal; This is done with respect to the lower and upper limits of the transducer's response range.

Similar to the prior art, the method according to the invention includes the step of detecting the occurrence of a digital word of a value representative of one of the limits of the A7D converter in a series of digital words over seven predetermined time lengths. The series of digital words is generated by an analog to digital converter over a predetermined length of time.

According to the invention, the detection step includes: (a) determining a first value representative of one limit of the response range of the A-D converter (e.g. all l);
The first number of that word in the sequence of digital words with
in a series of digital words with a second value (all zeros in this example) representing the lower limit of the response range of the A-to-D converter. (b) detecting within a predetermined length of time an occurrence of both a second and a number of the word of (the second number is equal to or exceeds a second threshold); and (b) at the end of the predetermined length of time. and performing a desired evaluation of the analog signal by means of the first and second occurrences detected at.

The analog signal calculation method of the present invention is used to adjust the limits of the analog signal to approximate the upper and lower limits of the A-D converter, or to adjust the DC level of the analog signal to the input limits of the A-D converter. It can be implemented in an AGO method to modify the amplitude of an analog signal or its DC level in order to adjust to some desired point within a range.

Hereinafter, a detailed explanation of the present invention will be given with reference to the figures.
Conversion circuit 12 has an input signal terminal S coupled to input terminal 14 . - By way of example, the A-D converter circuit 12 outputs all logical values 0 to 70 for inputs lower than 11 millivolts to an output terminal O connected to the output terminal 16 of the device.
It is assumed to be a 6-bit device that generates 6-bit words ranging from all logical values 1 to the 0-mi'J port input. The A/D conversion circuit 12 is coupled to a high peak detection circuit 1B and a low peak detection circuit 20 via multiplex cables (at least six lines). The multiplex cable is connected to a slash (A line) such as 22. A clock source 24 is coupled to each clock (c) terminal of the A-to-D conversion circuit 12, the high peak detection circuit 1, and the low peak detection circuit 20. ing.

At the occurrence of each clock pulse such as 26, A-'D
Conversion circuit 12 generates a six-pit word having a value representative of the amplitude of the voltage signal being applied to terminal 14. Regarding the six-pit A-to-D converter circuit illustrated, if the output signal from the A-to-D converter circuit 12 contains six "1"s, it essentially requires six input NAND gates and a timing circuit. The high peak detector 18, which consists of a high peak detector 18, generates an instantaneous logic O pulse as indicated at 2 days, and a logic level signal otherwise. If the signal generated by the A-D conversion circuit 12 contains 6 "0"s, 6
P, except that it contains input NOR gates.
Low peak detection circuit 18, similar to low peak detection circuit 1B, generates an instantaneous logic zero pulse as shown at 30 in response to six O's (instead of six ones), and otherwise outputs a logic level. generates a signal.

Detection circuit 18 is coupled to the count A terminal of first incrementing counter 40 . Counter 40 is connected to a high peak dual threshold detection circuit 42 having two output terminals HP and HP. Detector 42 operates according to rows 1 and 2 of Table I shown in FIG. 2, as will be explained in more detail below. Detector 42 is essentially a comparator that compares the count contained in counter 40 at a given time with a preselected set of high and low numbers, and a gate that generates the output signals shown in Table l. It consists of a logical device including:

Similarly, detector 20 is coupled to a second incrementing counter 46, which in turn is coupled to low peak detector 4B. Detector 4, which operates according to rows 3 and 4 of Table 1 of FIG. 2, has a similar structure to the previous detector 42.

The output HPFi of detector '42 is coupled to one input of AND gates 50 and 52, and the output HPFi is coupled to one input of AND gates 54 and 56.

The output LP of the detector 4 is connected to AND gates 50 and 56.
and the output π is coupled to second inputs of AND gates 52 and 54.

The update control circuit 60 is coupled to the clock input terminals C of the detectors 42 and 48, and via a short chain to the reset input terminals R of the counters 40 and 46, and to the reset input terminals R of the AND gates 50, 52, 54, and 56. and respective third inputs. As will be explained in more detail below, at an appropriate time circuit 60 generates an instantaneous pulse, as shown at 62, which clocks the counts of counters 40 and 46 into detectors 42 and 4B, respectively. and reset 46. At the same time, the detector 42
and 4B are energized by pulse 62 as shown in Table 2 of FIG.
One of the gates 50.52% 54 and 56 can be activated. This will be explained in more detail later. AND gates 50 and 54 are coupled to the amplifier input UP and down input DN of a third up/down binary counter 64. A, four-and-gates 52 and 56 are coupled to inputs UP, DN of a fourth up/down binary counter 66.

The counter 64 is coupled via multiple cables to the control terminals of the binary weighted switched attenuator 6. The input signal terminal 0 of the device, to which the analog signal to be digitized is supplied, is coupled to a current buffer 12. The output of current buffer 2 is coupled to the signal input of attenuator 68 of the automatic gain control circuit. The automatic gain control circuit comprises, in addition to the attenuator 6, a counter 64 and a fixed gain amplifier 6 to which the output of the attenuator 68 is coupled. Attenuator 6
Sun generally has a damping ratio of 3:1.

Since counter 6B is incremented by the signal passing through AND gate 50, the amount of attenuation in attenuator 68 increases, reducing the peak-to-peak amplitude of the signal passing through amplifier 76, thereby reducing the attenuation. The gain measured from the input of amplifier 68 to the output of amplifier 76 is reduced. Contrary to the above, when the count value of the counter 64 decreases due to the signal from the AND gate 54, the attenuation degree of the attenuator 6B decreases, and the peak of the signal passing through the amplifier 6B decreases.
Increase peak amplitude. In general, the counter 64 is one 6-pit counter, so the counter 64 is
can be set one after another to any of 64 damping ratios.

Counter 66 is coupled to a digital-to-voltage converter 8, which is also coupled to the (1) terminal of operational amplifier 80. The (to) terminal of the operational amplifier is coupled to receive the signal from the amplifier malo. The output of amplifier 80 is A- at terminal 14.
It is coupled to the input of D converter 12.

The A-to-D conversion device of FIG. It is designed to operate on a series of varying analog signals. The input signal is amplified by an amplifier 76 and further offset in amplitude by an amplifier 80 in a manner to be described below, and then sent to the A-D converter 1.
It is supplied to the input terminal 14 of No. 2. The input signal is then digitized by this A-D converter 12.

The operation of the circuit of FIG. 1 is as follows. Here, (a) terminal 14 is supplied with an analog signal having the same constant duration as the input, analog signal, supplied to terminal 0, and (b) the signal supplied to terminal 14 is explained later. Assume that the peak-to-peak amplitude and average DC level may be modified for the input analog signal in such a way that: Before the analog signal is applied to terminal 14, the pulse 62 from update control circuit 60
Detector 42 and 4B by the clock count value in 6
0 clock source 24 is, for example, 4.8 MH! ? A pulse of a predetermined constant frequency is generated. These clock pulses are applied to an A-to-D converter 12 which in turn generates a 6-bit digital word in response to the U clock pulses. Although not necessarily required, typically the portion of the analog signal applied to terminal 14 will be high enough such that A-to-D converter 12 will produce an output word of some number of six logic 1-pits. It is considered to be the amplitude. Similarly, although not necessarily required, the portion of the analog signal applied to terminal 14 is typically sufficient for A/D converter 12 to generate several output words of six logic 0 bits. It is assumed that the amplitude is low. If the signal applied to terminal 14 is related to the signal generated by the TV right camera, the six logic I states correspond to very bright parts of the scene, and the six logic zero states correspond to very bright parts of the scene. This corresponds to a very dark area.

For each output signal from A/D converter 12 consisting of all logic 1 bits, detector 18 generates a logic 0 pulse 2B under timing control of clock source 24. For each output signal of all logic zero bits from ADC 12, detector 20 generates a logic zero pulse 30 under timing control of clock source 24.

Counter 40 counts the number of pulses generated by detector IB with all logic ones, while counter 46 counts the number of pulses generated by detector 20 with all logic zeros. As previously mentioned, for a given duration of analog signal and constant frequency clock pulses provided by clock source 24, the total number of digital words generated by A-to-D converter 12 is known in advance. ing. When provided with any signal for which it is desired to use the full operating range of the A-D converter 12, a small portion or fraction of the total number of such digital words should all be logical; Also, all of the small parts or portions should be logic 0's. If all I words do not occur, and only all zero words occur, then the full digital range of A/D converter 12 is not utilized. Similarly, if too many all-logic I words and all-logic zero words are generated, the A-to-D converter will become saturated, producing distortion in any use of the digital words produced by the A-to-D converter 12. do. TV mentioned earlier
When using the right camera, experience has shown that the most favorable images are obtained when the frame contains 0.5% to 1.5% total logic l and l% to 2% total logic O. understood. Since the number of words generated by the A-D converter for such a series of analog signals is known and constant, the numbers representing the various percentages are also known and the counter decoder Alternatively, each detector 42 and 4 days are stored by wiring such as in memory.

As an example, assume that each analog signal is digitized by A-D converter 12 into 1000 words.

Therefore, the detector 42 stores the values 5 and 15, and the force detector 4B stores the values lO and 20. After the illustrative analog signal is applied to terminal 14 and digitized, an initial pulse such as 62 occurs and the value of counter 40 is clocked into detector 42 before the next analog signal is generated. , leads the value of counter 46 to detector 4. Then, counters 40 and 46 are incremented.

In the detector 42 - the number from the counter 40 is reduced to a fraction io, 5
Compare with numbers representing percent and 1.5 percent. Using values 5 and 15 and referring to Table 1 of FIG. 2, if the count of counter 40 is too high, i.e. greater than or equal to 15, terminal HP is set to a logic level and terminal HP is set to a logic 0 level. Set. Also, if the count of the counter 40 becomes high enough, i.e. 5
If less than or equal to, the terminal plane is set to a logic level and the terminal HP is set to a logic 0 level. Otherwise HP
, HP are both set to a logic 0 level.

Detector 4 and counter 46 operate in the same manner according to row 3, number of table l. After the above operations have taken place within four days of detector 42, a pulse 62 from update control circuit 60 energizes AND/G 50, 52, 54, and 54. The particular AND gate, if any, to be activated (at most only one AND gate is activated) is determined according to Table 2. For example, if both HP and LP are logic 1 (row 2 of Table 2), gate 5071i is activated and an analog signal outside the upper and/or lower limits that A-D converter 12 can handle. Indicates that there are too many. in this case,
According to row 2 of Table 2, counter 64 (which can be assumed to have been initially set by a previous modification condition to some arbitrary count value between its upper and lower limits) is advanced by l. The attenuation of attenuator 68 is thereby increased, the amplitude of the output of amplifier 16 is decreased, and the gain of the circuit consisting of the combination of attenuator 6 and amplifier 68 is decreased. Therefore, when the next analog signal is applied to terminal 10, the amplitude of the signal appearing at terminal 14 will be reduced relative to the amplitude of the preceding analog signal. Either there is no change from one analog signal to the next, or the signal at terminal 14 has no high and low peaks, as is the case with successive frame signals typically produced by a TV camera. It means that it does not contain it, or even if it does, it contains very little. Therefore, the counter 64 is decremented by l, the attenuation amount of the attenuator 6 becomes smaller, and the amplitude e of the signal at the output of the amplifier group 6 becomes larger than the preceding signal. It is increased so that it is amplified with a large gain.

If gate 52 is activated, the DC offset of the analog signal is too large and more than 1.5 percent of the digital signal from converter 12 is all logic 1s, causing A-
This means that less than one percent of the total words from D-converter 12 are all logic zeros.

Counter 66 is thereby incremented by l, the output voltage of converter 7B is reduced, and amplifier 80 is varied to reduce the DC offset imparted to the subsequent signal applied to the terminal. Finally, when the gate 56 is zeroed, the DC offset of the analog signal is very small and the 0.0 .
5% or less are all logic l, and A-D converter 1
This means that more than 2 percent of all words supplied from 2 are all logic 0's. Therefore, the counter 66 is l
, the output voltage of converter-y8 is increased and amplifier 80 is modified to provide a larger C offset to the subsequent signal applied to terminal 70.

If the condition continues for the next analog signal applied to terminal 14 (i.e., if the peak of the signal -
Peak amplitude over a very long period 1! (if the DC offset is very high or low, or if the DC offset is inappropriate), select an appropriate one of gates 50-56.
is energized again, and the power F of the counter 64 or 66 is
i is further increased or decreased after each successive analog signal applied to terminal F0 until neither gate is energized. counters 64 and 66
Both are of a type that neither increases beyond its upper limit count nor decreases beyond its lower limit count. Therefore, if the signal is outside the range of signals processed by the device, a distorted signal will be generated by the A/D converter 12. For purposes of explaining this invention, terminal '70
It is assumed that the nature of the signal supplied to the oscillator and the adjustment of the equipment are set such that no distortion conditions occur.

Then neither gate is energized (row 1 of table 2
16. 8.9) Explain the status. Row 1 shows a situation in which too many and not too many all logic 0 and all logic 1 digital words are generated, and amplifiers-16 and 8o are properly adjusted. That is, the signal supplied to terminal 14 is neither large nor small;
Also, rows 0, 6, 8, and 9, which are adjusted to a state that is not offset to an unfavorable state, are such that the signal supplied to the A-'D converter 12 is 8 illustrates conditions in which the output signal generates too many and too few all logic 1 digital words, and also generates too many and too few all logic 0 digital words. For the condition indicated by row 1 of Table 2, the series of analog signals is stored in counter 64 until the series of analog signals changes in content to an extent that requires readjustment of one or both of amplifiers 6 and 80 as described above. and 66 do not change.

In the situation represented by rows 6 to 9 of table 2,
No action is taken. However, (a) a condition in any one of these rows exists and the signal changes to a new amplitude, or to a new average level centered around the DC offset of the output of amplifier 80, and thus One of the states represented by rows 2 to 5 is (b) whereby the converter is in the operating state as described above and the output of the A-D converter 12 is transferred to rows 1, 2 of table 2,
6, 718 and 9.

The A/D converter of FIG. 1 is designed and described for situations in which the input analog signal appears as a series of burst signals;
a) supplying the actual number of words generated by the A-D converter 12 on the detector 42 and 4; and f) supplying the actual number of words generated by the A-D converter 12 on a periodic basis such as when the input pulse 62 occurs. By providing a detector adapted to calculate, it is also possible to operate in conjunction with continuous inputs.

As another variation, detector 42 and a number within four days may be supplied from A-'D converter 12 to a plurality (e.g. 10
00) may also be chosen to indicate the tolerance limit for the word. Under such conditions, A-D conversion 5
The number of words generated by 12 is the play number f6.
I'm jealous. . When the count value is reached,
The output of that counter can be used to generate the start pulse 62.

The gist of the invention is as shown in the claims, but it goes without saying that the invention described in the claims also includes the following embodiments.

(1) In the detection step, the first number of digital words is equal to or greater than a first threshold, and the second number of digital words is equal to or greater than a second threshold. The conversion method according to claim 1, wherein the conversion method has a value of .

(2) the detection step includes first and second signals (H
P%HP) and one of a third and fourth signal (LP, LP) indicative of the occurrence of a second number of digital words and the absence thereof, respectively. The conversion method described in (1) above, spanning the first term of the range.

(3) The detection step performs (1) a first count on the number of words with the τth value, and (6) a second count on the number of words with the second value. including that
The signal generation step also includes comparing the first and second count values with first and second thresholds, respectively (2) above.
Conversion method described.

(4) The received analog input signal consists of a series of burst-like signals having equal time lengths, and the time length of each burst-like signal is equal to a predetermined time length. and the conversion methods described in (1) to (3) above.

(5) The received analog input signal is continuous and the predetermined length of time is measured by the length of time required for the analog-to-digital converter to generate the predetermined number of words. 1. The conversion method described in item 1 and (1) to (3) above.

(6) adapted to control the amplitude of the analog signal to be measured, wherein the analog signal to be measured is derived by amplifying the received analog input signal with a variable gain amplifier; controlling the gain of the amplifier, the step of controlling the gain of the amplifier comprising: (1) decreasing the gain in response to occurrences of both the first and second predetermined numbers of digital words; The conversion method according to claim 1 and the above (1) to (5), characterized in that the conversion method operates to increase the gain in response to the absence of both the first and second predetermined numbers. .

()) configured to control the average DC level of the analog signal to be calculated, the signal to be calculated being derived through a step of controlling the received analog input signal according to the value of the digital word; The control step includes (1) the occurrence of a first predetermined number of digital words and a second predetermined number of digital words;
(6) the occurrence of a second predetermined number of digital words and the absence of a first predetermined number of digital words; 7. A conversion method as claimed in claim 1 and (1) to (6) above, comprising increasing the average DC level of the amplified analog signal in response to the presence of an amplified analog signal.

(8) detecting means, in response to the first and second count values reaching the first and second predetermined numbers, respectively, the first and second counts representing the occurrence of the first and second numbers of digital words, respectively; generating third control signals (HP, LP) [2 and in response to not reaching the first and second predetermined numbers, respectively; The second and fourth signals (HP,
3. The conversion device according to claim 2, wherein the control means is responsive to the first to fourth control signals.

(a) The detection means includes (1) a high peak detector (18);
an associated first increment counter (40) and a first high peak threshold detector (42”); and (6) a low peak detection 1 (2o) and an associated second increment counter (42”).
6) and a second low peak threshold detector (48), the inputs (22) of the high peak and low peak detectors
is coupled to the output of the analog-to-digital converter,
The high peak detector and low peak detector are respectively 1'
and the first and second counters generated by the analog-to-digital converter at the respective inputs (A) of the second counter.
a high peak threshold detector (42) and a low peak threshold detector (46) are operative to provide a signal for incrementing that counter in response to each digital word of value of the first and second The first and second count values in the counter are compared with the first and second predetermined values, respectively, and the first, second, third and fourth signals (HP, HP, L
The conversion device according to (8) above, which operates to generate (P, LP).

(lO) the amplification means includes a switched attenuator (6B) responsive to a digital signal; the control means includes first and second gates;
(50, 54') and the first up-down counter (
64), the first and second gates are configured to receive first and third signals (HPlLP) supplied from the high peak threshold detector and the low peak threshold detector, respectively, and the second and fourth signals ( HP, LP), and when energized, (
i) when both peak threshold detectors generate signals (HP and LP) representing the occurrence of a first and second number of digital words, generate a signal that increases the count of the up-down counter; 5) Decrease the count of the up-down counter when both peak threshold detectors generate a first and a second number of digital signals (HP and LP) representing the absence of the occurrence of a digital word. The control means (c) of the switching attenuator (68) are coupled to the output of the up-down counter and supplied to the input of the analog-to-digital converter in response to its count value. (a) above operating to control the amplitude of the analog signal;
The conversion device described.

(ll) the amplifying means comprises further means (80) responsive to a control signal supplied to the input (1) for adjusting the DC level of the amplified signal supplied to the input of the analog-to-digital converter; a control means (52, 56, 66, 78) coupled between the detection means and an input of said further means, wherein: (i) the amplified signal is responsive to the first and second signals; (b) adjusting the DC level of the amplified signal in response to the second and third signals toward the low level limit of the input of the analog-to-digital converter; The conversion device according to (8), (9), or (xo) above, characterized in that the conversion device is adjusted toward a high level limit of .

(12) Said further means include an operational amplifier (80) to which the amplified signal is supplied at one input (c); - this operational amplifier has at its output an amplified signal supplied to the other input; generating an amplified signal with a reference (pace) level controlled according to the level and feeding it to an analog-to-digital converter, the control means controlling the third and fourth gates (52, 5b); 2 up-down counter (6a) and a digital voltage converter (8), the third gate receives the first and fourth signals (HP , π),
The fourth gate is responsive to second and third signals (π, LP) also provided by high and low peak detectors,
generates signals for incrementing and decrementing the counts of the second up-down counter (66), respectively; ) to generate a voltage at its output at a level according to the count value of the second up-down counter, and the output voltage from the digital-to-voltage converter is applied to an operational amplifier (8
0). The conversion device according to (5) above.

(13) Update control means (60, D) is provided which operates at the end of a predetermined length of time, the update control means operating each peak threshold detector to 4 signals and then energizes the gates of the first and second incrementing counters (40, 46).
The above (
IO) or the conversion device according to (12).

[Brief explanation of the drawing]

FIG. 1 shows a preferred embodiment of an analog-to-digital converter constructed in accordance with the present invention in the form of an electrical circuit block diagram, and FIGS. 2 and 3 show an analog-to-digital converter of FIG. FIG. 3 is a diagram showing a table for explaining the operation of some circuits in the device in an easy-to-understand manner. 12...Analog-digital converter, 20...Input terminal, 68 C180 (1)...-Control terminal, 14
...Input of converter 12, 16...Output of converter 12, 18.20...Peak detection means, %FF Applicant RCI Corporation Director Satoshi Shimizu and 2 others + 72 Diagram tape) shi1 tape)shi2 one! Onika'JL/ Procedural amendment (spontaneous) 1. Indication of the case Patent Application No. 5'/-190663 2. Name of the invention Analog-to-digital conversion method and conversion device 3. Person making the amendment Relationship with the case Patent application Address New York, United States 1002
0 New York Rockefeller Frasa 30 names
(757) Rpeeney Corporation 4,
Agent 5, the fields to be amended: "Title of the invention,""Claims,""Detailed description of the invention," and "Brief description of drawings" in the specification. 6. Correct the contents of the amendment. (2. The claims are corrected as shown in the attached sheet. (4) The descriptions from page 26, line 17 to page 3, line 13 of the same book are deleted. (5) The specification has been changed to the following errata. Attachment Document Claims Exceeding Patent Claims l) In a method for calculating one or both of the amplitude and the average DC level within a predetermined time length of an analog signal, the above calculation is performed when the analog signal is supplied. Analog to be done
The analog-to-digital converter is operated with respect to the low-level and high-level limits of the response range of the digital converter, and is operated on a series of digital carcasses produced by the analog-to-digital converter over a predetermined length of time. detecting over the predetermined period of time the occurrence of a digital word having a value representative of one of the level limits; (5) generation of a first predetermined number of digital words having a first value; and (5) a second predetermined number of digital words having a second value representative of the lower limit of the response range of the analog-to-digital converter. Detection of word occurrences is performed, thereby making predictions

Claims (2)

[Claims] (1) In a method for calculating the amplitude and/or average DC level of an analog signal within a predetermined length of time, the above calculation is based on the low level limit and the high level limit of the response range of the analog-to-digital converter to which the analog signal is supplied. is carried out with respect to the level limit, and is a digital word whose value is representative of one of said analog-to-digital converters within a series of digital words produced by said analog-to-digital converter over a predetermined length of time. detecting occurrence of a word over the predetermined period of time. The detection step includes: within the series of digital words: (i) the occurrence of a first predetermined number of digital words having a Jth value representative of the upper limit of the response range of the analog-to-digital converter;
and (b) detecting the occurrence of a second predetermined number of digital words having a second value representative of the lower limit of the response range of the analog-to-digital converter, thereby detecting the occurrence of a second predetermined number of digital words at the end of the predetermined length of time. An analog-to-digital conversion method, wherein an analog signal is calculated by the lifetime of the first and second predetermined numbers of digital 211 words. (2) A device for adjusting one or both of the amplitude and direct current level of a received input analog signal related to the upper and lower limits of the input range of an analog-to-digital converter, which amplifies the supplied input analog signal and
first means having control terminal means for controlling an analog signal supplied to a digital converter; and between the output of said analog-to-digital converter and the control terminal means of said first means for amplification. coupled detection means and control terminal means of the first means for amplification, the detection means being coupled between the detection means and the control terminal means of the first means for amplification; control means for generating a control signal provided to the means, wherein said analog-to-digital converter is responsive to an amplified signal provided to its input from said first means for generating a sample of said signal. producing at its output a series of digital output words having values that are a function of the first and second digital words; A digital-to-analog conversion device for generating control signals representative of first and second occurrences in response to the count reaching first and second predetermined numbers, respectively.