JPS5883390A - Rom output reading circuit - Google Patents

Abstract

PURPOSE:To supply an accurate readout output, by latching an ROM output in two stages at prescribed timing and thus performing accurate latching operation before the ROM output is discharged. CONSTITUTION:The readout output of an ROM11 is latched by the 2nd latch circuit 32 through the 1st latch circuit 31. This circuit 31 is controlled by the AND output signal phiA of a clock and a delay control signal delayed by the time which is one basic cycle of reading operation shorter then generation intervals of a readout instruction control signal from a computer. Therefore, the precharging of the ROM11 is controlled to perform accurate latching after one basic cycle in which reading operation is made possible and before the readout output from the ROM11 is discharged, so that even when the control cycle period of the computer side is long, the readout output of the ROM is supplied accurately through the circuit 32.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ROM output read circuit for latching the output of a ROM (read only memory).

Figure 1 shows, for example, the i-microcombi tool - 110 in the evening.
This shows a conventional example of the M section, and 11 includes, for example, a Guichuck type Royx, an xzh address decoder, and an IJ enlarged output latch circuit.

φ, □Precharge signal of address decoder/12, φ
1° is the precharge signal of ROM JJ, φ1 is the latch signal of the latch circuit 13, φ1 is the address decoder 1
z drive signals, and these are generated at the timing shown in FIG. 2, for example.

In the table or Figure 2, φ and φ are two-phase clocks, and 9, RTN is the last basic cycle of a certain instruction cycle of the CPU of the micro combiator, and is generated in synchronization with the four clocks φ1 mentioned above. control signals such as return signals, RT
Nl is a return signal obtained by delaying the above RTN until the time corresponding to the above RTN until the time corresponding to the above RTN.
, is a return signal in which the RTN 1 is delayed until the clock φ3 following the clock φ1 corresponding to the RTN, in other words, the RTN is delayed by one bit (basic cycle). Here, the drive signal φ1 is a return signal RTN.

and clock φ! The latch signal φ8 is an AND output of the return signal RTN1 and the clock φ.

In the ROM section, the return signal RTN.

After precharging the precharge signal φADI 'φ1゜to the seat address decoder 12 and ROM 111) Z, the drive signal φ1 and the seat address input signal A respond to the drive signal φ1 and the seat address decoder 12 and ROM 11 (!> address specification is performed, and ROM JZ becomes ready for output.

Then, according to the next generated latch signal φ1, ji) RO
It is latched by the output latch circuit 13 of M11.

By the way, when the return signal RTN is generated at an interval of 4 bits (for example, 1 machine cycle) as shown in FIG.
Since this occurs 4 bits after the ROM 11 becomes ready for output, it can be latched before the ROM output is discharged. However, in processing a certain opcode, the return signal R
There are cases where TN is 8 bits (for example, 2 machine cycles) and occurs only K1 times, in which case the return signal R
TN1 e nTN*, drive signal φ7, latch signal φ
1, precharge signal φADI #φ,. However, each bit occurs only once every 8 bits. Therefore, when the latch signal φ8 is generated 8 bits after the drive signal φ1 enables the ROM IJ to output,
If the ROM output is discharged, normal latching may not be performed.

That is, conventionally, the control signal (return signal RTN in this example) involved in determining the ROM read timing was
If this occurred irregularly, such as once every bit or once every 8 bits, it was not possible to double the normal KROM output.

The present invention has been made to eliminate the above-mentioned drawbacks, and the RO
Even if the control signals involved in determining the read tie setting of M are generated irregularly, the minimum interval of their generation is also R.
The 9 ROM output is latched by the first latch signal, which is delayed by one basic cycle of the OM read operation, and the above-mentioned latch contents are latched and outputted by the second latch signal prior to the next address specification. A ROM that can accurately latch ROM output by performing two-stage latching.
It provides an output readout circuit.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The ROM output readout circuit shown in FIG. 3 differs from the circuit described above with reference to FIG.
1) The latch signal φ8 is supplied to the first circuit 32, and the latch signal φ, which is the AND output of IRTNs and the clock φ1, is output from the minimum interval (4 bits) of the generation interval of the return signal RTN. (The difference is that the supply is supplied to the latch circuit J1), otherwise the same parts as in FIG. 1 are designated by the same reference numerals in FIG. Omit the description. Incidentally, the second latch circuit 32 companies are referred to as the latch circuit 13 shown in FIG.

In the above configuration, even if the return signal RTN is generated every 8 bits as shown in FIG. latch signal φ, 9
Since the ROM output is latched by the first latch circuit S1,
Data is not lost due to discharge of the ROM output, and latching is performed normally. Then, following the latch signal φ, as shown in FIG. 4, in this example, the latch signal φ is generated by timing φ10 of the clock 6 bits later than the clock φ. The output of 31 is doubled by the second latch circuit 22 and output as a readout output.

If the return signal RTN is generated every 4K bits as described above with reference to FIG. At the timing of the subsequent clock φ1, racking is performed using the latch signal φ1, and at the timing of the next clock φ1, the next address is specified using the drive signal φ1. Normal latching occurs before discharge.

As described above, according to the ROM output readout circuit of the present invention,
Even if the return signal occurs irregularly, such as once every 4 bits or once every 8 bits, it will be one basic cycle shorter than the minimum interval between the generation of the return signal RTN after the ROM becomes ready for output. After a time, the first latch signal φ.

Since the i ROM output is latched and the latched contents are latched and outputted by the second latch signal φ1 prior to the next address specification, the ROM output is discharged. It is possible to accurately latch the circuit before it is lost, the readout output is accurate, and normal operation of a microphone combinator or the like using this circuit can be obtained.

FIG. 1 is a block diagram showing a conventional ROM output readout circuit.
2 is a timing chart shown to explain the operation of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the ROM output readout circuit according to the present invention, and FIG. 4 is shown to explain the operation of FIG. 3. FIG.

11... ROM, 31... first latch circuit, j! −
...Second latch circuit.

Claims (1)

[Claims] A first latch is provided on the output side of the ROM (read only memory) and latches the 9 ROM output by the first latch signal.
a latch circuit, a second latch circuit that latches the output of the first latch circuit with a second latch signal, and a minimum interval between generation of the control signal for determining the read timing of the ROM; generating the first latch signal (by means of generating a delayed control signal delayed by one basic cycle of a ROM read operation for a short period of time, and by logical processing of the delayed control signal and the first phase clock by this means); and a second phase readout circuit which is delayed by one cycle from the generation timing of the control signal.