JPS5882520A - Manufacture of ohmic electrode in electron device - Google Patents
Manufacture of ohmic electrode in electron deviceInfo
- Publication number
- JPS5882520A JPS5882520A JP18051881A JP18051881A JPS5882520A JP S5882520 A JPS5882520 A JP S5882520A JP 18051881 A JP18051881 A JP 18051881A JP 18051881 A JP18051881 A JP 18051881A JP S5882520 A JPS5882520 A JP S5882520A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- silicide
- melting point
- substrate
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 48
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 47
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000002844 melting Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000008018 melting Effects 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 13
- 238000000059 patterning Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 17
- 239000007789 gas Substances 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910000510 noble metal Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000010406 interfacial reaction Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241000981595 Zoysia japonica Species 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 101100310622 Mus musculus Soga1 gene Proteins 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000033001 locomotion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
- 230000029305 taxis Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路等に代表される電子デバイスのオーミ
ック電極の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing ohmic electrodes for electronic devices such as integrated circuits.
集積回路等の電子デバイスにおいては、近年、高速度化
及び高密度化の要請から、素子寸法の32次元的な縮少
が行われてきた。この九めに、オー建ツク電極下に形成
されるpm接合の接合深さは数千λ以下に形成される様
になりた。現在、集積回路のコンタクトメタルとしては
アルミニウム(以下AIと略す)の蒸着薄膜が最も広く
用いられているが、膜厚l声IK程度以下の接合深さの
pn接合上のコンタクトメタルとしてAI薄膜を用い九
場合には、蒸着後に行う450℃程度の熱処理時に、p
n接合の短絡による不良が発生することが知られている
。これは、前記熱処理時に生ずる基板シリコン(以下8
Mと略す)とAIとの相互拡散に起因しているが、この
拡散が均一に生じないために人lが基板si中へ局所的
に深く進入することによっている。In recent years, in electronic devices such as integrated circuits, element dimensions have been reduced by 32 dimensions due to demands for higher speed and higher density. Nineteenth time, the depth of the pm junction formed under the open electrode has come to be less than several thousand λ. Currently, vapor-deposited thin films of aluminum (hereinafter abbreviated as AI) are most widely used as contact metals for integrated circuits. In case of use, p
It is known that defects occur due to short circuits in n-junctions. This is due to the substrate silicon (hereinafter referred to as 8
This is due to the interdiffusion between AI (abbreviated as M) and AI, but because this diffusion does not occur uniformly, the particles locally penetrate deeply into the substrate si.
従来よ)、前記不良を防止する試みとしては以下に示す
2つの方法が採られてきた。一つは、コンタクトメタル
として純粋なAIを使用する代シに、固溶限界をわずか
に上回る数重量パーセント程度の8iをあらかじめ含ん
だAIからなる組成物を用いる方法である。確かに、当
該組成物からなるコンタクトメタルを使用した場合には
、純粋なAIを用いた場合と異って、450℃程度の熱
処理では前記した接合の不良を生じさせない。しかし、
本発明者が行った実験では、コンタクト抵抗値の絶対′
値およびバラツキを望み通シ小さく抑えるためには、熱
処理温度を400℃から475℃程度の範囲に選択する
必要があり、500℃以上の熱処理を行った場合、コン
タクト抵抗の増大がみられ、界面での固有接触抵抗値は
一桁以上上昇する。この様な熱処理温度における制限は
以下に記す点で大きな不都合を生ずる。Conventionally, the following two methods have been adopted in an attempt to prevent the above-mentioned defects. One method, instead of using pure AI as a contact metal, is to use a composition made of AI that already contains 8i in an amount of several percent by weight, which is slightly above the solid solubility limit. It is true that when a contact metal made of this composition is used, heat treatment at about 450° C. does not cause the above-mentioned defective bonding, unlike when pure AI is used. but,
In experiments conducted by the present inventor, the absolute value of the contact resistance value
In order to keep the value and variation as small as desired, it is necessary to select the heat treatment temperature in the range of about 400°C to 475°C. If heat treatment is performed at 500°C or higher, contact resistance increases and the The specific contact resistance value increases by more than an order of magnitude. Such restrictions on the heat treatment temperature cause major disadvantages in the following points.
従来のMO8集積回路の製造方法では、AI薄膜形成後
における通常のパターニングけ、光学露光法と湿式エツ
チング法との組合せによりて付勢れてきたが、1〜2μ
m程度以下の鍾小寸法を持つ微細配線パターンにはもは
や適用が不可能となシ、かかる微細パターンのバターニ
ングには、電子ビーム露光法とドライエツチング法との
組合せが有効である。これらの製造方法の変更にともな
って以下に記す新ら九な問題が生じた。すなわち電子ビ
ーム照射時に、MO8界面等に誘起された損傷に起因し
て、界面単位中固定電荷の発生がみられ、閾値電圧の変
動等が生じたシ、ゲート酸化膜中には中性トラップが形
成されることにより信頼性上の問題が生じたりすること
が知られる様になった。これらの損傷の回復には従来の
450℃程度の熱処理では不十分であり、500℃以上
の熱処理が必要となる。しかし、前記した様に、数重量
パーセントのSiを含んだA1薄膜をコンタクトメタル
として使用したオーミック電極に5001〕以上の熱処
理を実施した場合にはコンタクト抵抗が著しく増大する
欠点が生じる。In the conventional manufacturing method of MO8 integrated circuits, the patterning after forming the AI thin film and the combination of the optical exposure method and the wet etching method were used.
This method can no longer be applied to fine wiring patterns having dimensions of about 500 m or less, and a combination of electron beam exposure and dry etching is effective for patterning such fine patterns. With these changes in manufacturing methods, nine new problems have arisen as described below. In other words, due to damage induced at the MO8 interface during electron beam irradiation, fixed charges were generated in the interface unit, fluctuations in threshold voltage, etc. occurred, and neutral traps were generated in the gate oxide film. It has become known that reliability problems may arise due to the formation of Conventional heat treatment at about 450° C. is insufficient to recover from these damages, and heat treatment at 500° C. or higher is required. However, as described above, when an ohmic electrode using an A1 thin film containing several weight percent of Si as a contact metal is subjected to a heat treatment of 5001] or more, a disadvantage arises in that the contact resistance increases significantly.
もう一つの方法は、基板SiとA1薄膜との間にPd、
Pt 等の貴金属のシリ伊イド、またはTa。Another method is to use Pd between the Si substrate and the A1 thin film.
silicides of noble metals such as Pt, or Ta.
Mo等の高融点金属のシリサイドを介在させることによ
って基板81と人1との相互拡散を防ぐ試みである。し
かしながら前者の貴金属シリサイドを介在させ九オーず
ツク電極に400℃の熱処理を行った場合、AI とシ
リサイドとの間の反応が生じ、シリサイド層は消滅しA
l5Pd、A15Pt等の化合物が形成され、かつ、A
15Pd、AlgPtを介してA1と81との相互拡散
が生じる。従って500℃以上の熱処理では、Pn接合
の短絡やリークが発生し、オーミック電極としては有用
でない。This is an attempt to prevent mutual diffusion between the substrate 81 and the person 1 by interposing silicide of a high melting point metal such as Mo. However, when the former noble metal silicide is interposed and a 400°C heat treatment is applied to the nine oscilloscope electrode, a reaction occurs between AI and the silicide, and the silicide layer disappears.
Compounds such as l5Pd and A15Pt are formed, and A
Mutual diffusion between A1 and 81 occurs through 15Pd and AlgPt. Therefore, heat treatment at 500° C. or higher causes short circuits and leaks in the Pn junction, making it unusable as an ohmic electrode.
一方、Ta、Mo等の高融点金属のシリサイドを介在さ
せたオーミック電極では前記した貴金属シリサイドを介
在させた場合に比較して、A1 とシリサイドを構成す
る金属との化合物形成が始まる温度はより高温となって
いるが、以下に記述する様に500℃以上の熱処理にお
ける耐熱性にはやはり問題かある。On the other hand, in the case of an ohmic electrode in which a silicide of a high-melting point metal such as Ta or Mo is interposed, the temperature at which the compound formation between A1 and the metal constituting the silicide begins is higher than in the case of intervening the above-mentioned noble metal silicide. However, as described below, there is still a problem with the heat resistance in heat treatment at 500° C. or higher.
ジー、ジェイ、ファン、ガルプ(G、 J 、 van
Qurp)氏等は、ジャーナル・オプ・アプライドフィ
ジックス(Journal of Applied P
hysics)金弟50巻第11号第6915〜692
6頁(1979年11月)において、81基板上にMo
膜をスパッタリングによって堆積した後、HlガスとN
雪ガスとの混合ガス雰囲気において、600℃の熱処理
を行うことによ、9,2500λの膜厚のMo8i*を
形成し、上部に電子銃蒸着によって膜厚soo。G, J, van
Qurp et al., Journal of Applied Physics (Journal of Applied Physics)
hysics) Golden Brother Volume 50 No. 11 No. 6915-692
6 (November 1979), Mo
After depositing the film by sputtering, Hl gas and N
By performing heat treatment at 600° C. in a mixed gas atmosphere with snow gas, Mo8i* with a film thickness of 9,2500λ is formed, and a film thickness of soo is formed on the top by electron gun evaporation.
λの人!薄膜を形成しえ試料に534℃、30分間の熱
処理を行っ先後、上部のAIをエツチングして、界面反
応を詳細に検討した結果を報告している。その報告では
、81成分の多い大きな粒子の成長がみられること及び
いくつかのピットがみられることよシ界面反応が生じて
いると判断しておシ、成長し九81粒子の形成機構とし
ては、81の固相エピタキシーにおける8iの移送機構
と類似性があり、シリサイドの結晶粒界を通して基板を
構成するs量が拡散されたためとしている。まえ、ビッ
トの発生原因としては、Mo1ls膜内のピンホールに
起因して、SMのAl中への拡散が生じている仁とを挙
げている。さらに、同報告では、前記構造とほぼ同様な
構造に545℃1時間の熱処理を行った後に、後方散乱
法によってMo。λ person! After forming a thin film on the sample and subjecting it to heat treatment at 534°C for 30 minutes, the upper AI was etched, and the results of a detailed study of the interfacial reaction are reported. In the report, it was determined that an interfacial reaction was occurring based on the growth of large particles containing many 81 components and the presence of several pits. , 81 is similar to the transport mechanism of 8i in solid phase epitaxy, and it is thought that the amount of s constituting the substrate is diffused through the grain boundaries of silicide. Previously, the cause of the bit generation was cited as the diffusion of SM into Al due to pinholes in the Mo1ls film. Furthermore, in the same report, a structure similar to the above structure was heat-treated at 545° C. for 1 hour, and then Mo was analyzed using a backscattering method.
AI等の原子の移動を調べた結果において、ごくわずか
のMoしか表面のAl中へ移動していないことを報告し
ている。従って、熱処理による電極の劣化はMOとAI
との化合物形成の反応よりはむしろ、Monj!の多
結晶性及び不均一性に起因しているものと判断される。As a result of investigating the movement of atoms such as AI, it has been reported that only a small amount of Mo moves into the Al on the surface. Therefore, electrode deterioration due to heat treatment is caused by MO and AI.
Rather than reacting to form a compound with Monj! This is considered to be due to the polycrystalline nature and non-uniformity of the material.
また、x、x、・ビー・ムラルカ(8−P −Muri
rka)氏がジャーナル・オプ・バキユーム・サイエン
ス・アンド・テクノロジー(Journal of V
acuum 5cienceand Technolo
gy )総画17巻、第4号第775〜792頁(19
80年8月)にTaxisをAtと基板81 との間に
介在させ九構造に300’〜500℃の熱処理を行った
後の界面反応の結果について報告しているが、その結果
では、いかなる界面反応も生じていない。従って、前記
した貴金属のシリサイドを介在させた場合よシ耐熱性は
向上してaるが、しかし、500℃以上での実験結果の
報告はなく、500℃以上の熱処理に耐えちるかどうか
は不明である。以上の様に、現在、A1薄膜形成後に5
00℃以上の熱処理に耐えうるAt系電極はない。In addition, x, x, B Muraruka (8-P -Muri
rka) is the author of the Journal of Vacancy Science and Technology (Journal of V.
acum 5science and technology
gy) Soga Volume 17, No. 4, pp. 775-792 (19
(August 1980) reported on the results of interfacial reactions after heat treatment at 300' to 500°C on the 9 structure with Taxis interposed between At and the substrate 81; No reaction occurred. Therefore, heat resistance is improved when the noble metal silicide mentioned above is interposed, but there are no reports of experimental results at temperatures above 500°C, and it is unclear whether it can withstand heat treatment at temperatures above 500°C. It is. As mentioned above, currently, after forming the A1 thin film,
There is no At-based electrode that can withstand heat treatment at temperatures above 00°C.
本発明はかかる事情に鑑み、500℃以上の熱処理に耐
えうるAt系オーミック電極の製造方法を提供すること
にある。In view of the above circumstances, the present invention provides a method for manufacturing an At-based ohmic electrode that can withstand heat treatment at 500° C. or higher.
本発明者はムl薄膜と基板81 との間に介在さる高融
点金属のシリサイドの形成方法と金属学的性質との関連
を詳細に検討した結果、本発明を導出するに致っ九。高
融点金属のシリサイドの従来の形成方法としては、前記
したジー・ジエイ・ファン・ガルプ(G−J・マan
Qarp )氏の報告に与られる様に、基板1上に高融
点金属層を形成した後600℃付近の温度で熱処理を行
って形成する方法が知られているが、本発明者は基板S
N上に薄い高融点金属層を形成した後、イオン注入を行
い、その後、600℃付近で熱処理を行うことによって
シリサイド層を形成し、それらのシリサイドの金属学的
性質を従来法によって形成されたシリサイドの金員学的
性質と比較検討した結果両者の形成方法によって得られ
るシリサイドの金属的性質が大きく異なることをみいだ
した。イオン注入は、基板81上に形成した350大の
膜厚のMO膜を通して、ムlイオンを□加速電圧160
key でドーズ量2X1G”−罵°″ だけ行っ
た。The present inventor conducted a detailed study on the relationship between the metallurgical properties and the method of forming a high melting point metal silicide interposed between the thin film of mulch and the substrate 81, and as a result, the present invention was developed. Conventional methods for forming silicides of high-melting point metals include the above-mentioned G.J.
As reported by Mr. Qarp), a method is known in which a high melting point metal layer is formed on the substrate 1 and then subjected to heat treatment at a temperature of around 600°C.
After forming a thin high-melting point metal layer on N, ion implantation is performed, followed by heat treatment at around 600°C to form a silicide layer, and the metallurgical properties of these silicides are compared to those formed by conventional methods. As a result of a comparative study of the metallurgical properties of silicides, we found that the metallic properties of the silicides obtained by the two methods of formation differ greatly. The ion implantation is carried out by introducing Mul ions through an MO film with a thickness of 350 mm formed on the substrate 81 at an acceleration voltage of 160 mm.
key was used at a dose of 2X1G"-".
従来法では表面に多数の微細構造がみられるの対し、後
者の方法では微細構造はみられない。この差異をさらに
詳しく検討するために、走査型電子顕微鏡および透過電
子顕微鏡による表面の観察を行ったが、走査型電子顕微
鏡では、従来法で形成したMoシリサイドの表面は微細
構造に対応した表面の凹凸がよく観察されたが、後者の
イオン注入を利用して形成したMoシリサイドの表面は
非常に平坦であり、表面の凹凸は観察できなかった。In the conventional method, many microstructures are observed on the surface, whereas in the latter method, no microstructures are observed. In order to examine this difference in more detail, we observed the surface using a scanning electron microscope and a transmission electron microscope.The scanning electron microscope revealed that the surface of Mo silicide formed by the conventional method had a surface that corresponded to the microstructure. Although unevenness was well observed, the surface of the Mo silicide formed using the latter ion implantation was extremely flat, and no surface unevenness could be observed.
これらの事実は透過電子顕微鏡写真によってさら 0に
裏付けられる。従来法で形成されたMoシリサイドは、
数G^の粒径の微小粒の集合よりなる多結晶膜であるの
に対し、後者のイオン注入を利用して形成したMoシリ
サイドは結晶粒界のない単結晶状膜であることが判る。These facts are further supported by transmission electron micrographs. Mo silicide formed by the conventional method is
It can be seen that the Mo silicide formed using the latter ion implantation is a single-crystalline film without grain boundaries, whereas the film is a polycrystalline film made up of a collection of minute grains with a grain size of several G^.
また、表面の平坦性や均−性感イオン注入を利用して形
成したMoシリサイド膜の方が極めて良好である。Furthermore, a Mo silicide film formed using ion implantation with a high surface flatness and uniformity is much better.
本発明は電極を形成すべきSi基板表面に膜厚500λ
以下の高融点金属層を形成する工程と、該高融点金属の
上部よりイオン注入を行った後、600℃付近の熱処理
を行ない、未反応な高融点金属をエツチングし高融点金
属のシリサイド層を前記露出旧表面に選択的に形成する
工程と、800℃以上の温度で熱処理を行う工程と、前
記シリサイド表面の1部分にAI電極配線を接触させる
工程とを含むことを特徴とするものである。The present invention has a film thickness of 500λ on the surface of a Si substrate on which electrodes are to be formed.
After the following process of forming a high melting point metal layer and performing ion implantation from above the high melting point metal, heat treatment is performed at around 600°C to etch the unreacted high melting point metal and form a silicide layer of the high melting point metal. The method is characterized by comprising the steps of selectively forming the silicide on the exposed old surface, performing heat treatment at a temperature of 800° C. or higher, and bringing an AI electrode wiring into contact with a portion of the silicide surface. .
イオン注入を利用して形成した前記の種々の特長を持つ
九Moシリサイド等の高融点シリサイド層を人l薄膜と
基板s量との間に介在させてオー建ツク電極を形成し、
450”〜550℃の熱処理を行い耐熱性を検討した結
果、500℃以上でも接触抵抗が十分小さい曳好なオー
宅ツ夛電極が得られることが判り九。A high melting point silicide layer such as Mo silicide, which is formed using ion implantation and has the above-mentioned various features, is interposed between the thin film and the substrate to form an open electrode.
As a result of conducting heat treatment at 450'' to 550°C and examining the heat resistance, it was found that a highly conductive, self-contained electrode with sufficiently low contact resistance could be obtained even at temperatures above 500°C.
以下、本発明の典型的な一実施例について図面を用いて
詳細に説明する。Hereinafter, a typical embodiment of the present invention will be described in detail using the drawings.
第1図(a)〜(d)は本発明の製造工程の1例を示し
た概略断面図である。FIGS. 1(a) to 1(d) are schematic cross-sectional views showing one example of the manufacturing process of the present invention.
If、7り−にフ#ll)&6.5X10”car−”
ノル型8i基板11を用意し、この基板を酸素雰囲気
中で酸化し、約4oooAの膜厚の酸化膜12を成長さ
せた後、ホトレジストをマスクとして酸化膜12をエツ
チングし、8i基板表面13を露出させる(第1図(a
))。If, 7 years ago #ll) &6.5X10"car-"
A nor-type 8i substrate 11 is prepared, and this substrate is oxidized in an oxygen atmosphere to grow an oxide film 12 with a thickness of approximately 4oooA.The oxide film 12 is then etched using a photoresist as a mask, and the surface 13 of the 8i substrate is etched. Expose (Figure 1 (a)
)).
次に、膜厚100λのMo膜14をスパッタ蒸着によっ
て形成し、上部よりA8イオンを加速電圧100keV
でドーズ量5X10”cm−” 注入する。この後、H
sガス雰囲気で600℃、20分間の熱処理を行うとコ
ンタクトが形成されるべきn+層15の表面上のみにM
oシリサイド16が形成される(第1図(b))。Next, a Mo film 14 with a thickness of 100λ is formed by sputter deposition, and A8 ions are applied from above at an acceleration voltage of 100 keV.
Inject at a dose of 5 x 10"cm-". After this, H
When heat treatment is performed at 600°C for 20 minutes in an S gas atmosphere, M is formed only on the surface of the n+ layer 15 where a contact is to be formed.
o-silicide 16 is formed (FIG. 1(b)).
次に、HsOz系エツチング液によって酸化膜上のMo
をエツチングを行う。この時、Moシリサイド16はエ
ツチングされないために、コンタクトが形成されるSi
表面上のみにMoシリサイド16が選択的に形成される
(第1図(C))。Next, Mo on the oxide film is removed using HsOz-based etching solution.
Perform etching. At this time, since the Mo silicide 16 is not etched, the Si where the contact is formed
Mo silicide 16 is selectively formed only on the surface (FIG. 1(C)).
この後、N!中で1000℃、20分間の熱処理を行っ
て、注入され九λ$イオンの活性化を行う。次に、膜厚
1μmのAl17を蒸着し先後、通常の方法によってバ
ターニングを行って第1図(d)に示す構造のオー建ツ
ク電極が完成される。After this, N! The implanted 9λ$ ions are activated by heat treatment at 1000° C. for 20 minutes. Next, Al17 with a thickness of 1 .mu.m is deposited and then patterned by a conventional method to complete an oak-shaped electrode having the structure shown in FIG. 1(d).
本実施例では、薄いMo膜を通してAs注入を行ってM
oシリサイドを形成した場合について記述し九が、Pイ
オンの場合にも同様に有効である。In this example, As is implanted through a thin Mo film to
9, which is described for the case where o-silicide is formed, is similarly effective in the case of P ions.
本発明によって形成したオー建ツク電極をH3ガス雰囲
気において450℃〜550℃の範囲で3゛0分間の熱
処理を行った後に得られたコンタクト界面における固有
接触抵抗は〜1O−69d程度でほぼ一定であり、s0
0℃を越える熱処理時にもコンタクト抵抗の著しい上昇
はみられなかった。The specific contact resistance at the contact interface obtained after heat-treating the oak-structured electrode formed according to the present invention at a temperature of 450°C to 550°C for 30 minutes in an H3 gas atmosphere is approximately constant at ~1O-69d. and s0
No significant increase in contact resistance was observed even during heat treatment above 0°C.
また、Pn接合の短絡の発生もみられなかった。Further, no short circuit of the Pn junction was observed.
本発明によれば、A1電極配線形成後に550℃までの
熱処理を実施してもよく、従来法に比較して、AI電極
配線形成後に実施する熱処理の耐熱性が向上しているこ
とが明らかである。このため従来法では電子ビーム照射
等に起因した損傷の回復を十分に行う熱処理を実施する
ことができないのに対し、本発明では、500℃以上の
熱処理によって損傷の回復を十分に行うことができると
いう点で大きな改善が示されている。According to the present invention, heat treatment up to 550° C. may be performed after forming the A1 electrode wiring, and it is clear that the heat resistance of the heat treatment performed after forming the AI electrode wiring is improved compared to the conventional method. be. For this reason, in the conventional method, it is not possible to perform heat treatment to sufficiently recover damage caused by electron beam irradiation, etc., whereas in the present invention, damage can be sufficiently recovered by heat treatment at 500°C or higher. Significant improvements have been shown in this respect.
なお、前記実施例では介在させる高融点金属としてMo
シリサイドを用いた場合について記載したが、例えばW
、Ti 、Ta 轡のシリサイドを用いた場合にも同
様な卓効があることがVめられた。In addition, in the above embodiment, Mo was used as the intervening high melting point metal.
Although the case using silicide has been described, for example, W
, Ti, and Ta silicides were found to have similar effectiveness.
第1図(a)〜(d)は、本発明の一実施例の製造工程
を示した概略断面図である。
11・・・・・・81基板、12・・川・酸化膜、13
・・団・コンタクトを形成すべき亀山旧表面、14・・
・・・・Mo Ks 1s・・・・・・n”L 16・
・・・・・Moシリサイド、′17・・川・A1電極配
線。
v−1功
手続補正書輸発)
57.6.23
昭和 年 月 日
特許庁長官 殿
1、事件の表示 昭和s6年 特 許 願第180
518号2、発明の名称 電子デバイスのオー竜
ツク電極の製造方法3、補正をする者
事件との関係 出 願 人東京都港区芝五
丁目33番1号
4、代理人
〒108 東京都港区芝五丁目37番8号 住友三田
ビル日本電気株式会社内
(6591) 弁理士 内 原 晋電話東京(0
3)456−3111(大代表)(連絡先 日本電気株
式会社特許部)
5、補正の対象
明細書の特許請求の範囲の欄。
明州書の発明の詳細な説明の欄。
6、11i正の内容
(1)特許請求の範囲の欄を別紙のように補正する。
(2)明細書t1M5頁第5行目にr Pn接合」とあ
るのをrpn接合」に補正する。
(3) 明細書第8頁第5行目に「致ったーとあるの
を「到った。」に補正する。
に補正する。
(5)明細書第10頁第1行目に「600℃付近の熱処
理を行ない、」とあるのをr 400−60Q℃の熱処
理を行ない、」に補正する。
(6)明細書第10頁第4行目に「℃以上の温度で熱処
理を行う工程と、」とあるのを「℃以上の温度で非還元
性ガス雰囲気中で熱処理を行う工程と」に補正する。
(7) 明−書簡10頁第6行目の「とするものであ
る。」のIIK、次の文章を挿入する。
本発明の方法では、イオン注入を行った後に400−6
00℃と−う比較的低温の熱処理を行い、この後未反応
な高融点金属を除去した後に800℃以上の熱処理を行
う2段熱娘理法が行われているが、この2段熱処理は均
一かつ、平滑な高融点金属珪化物を電極を形成すべきシ
リコン表面に対して自己整合的に形成する上で、極めて
重要である。
す々わち、イオン注入後の最初のアニールを、例えば、
800℃程度以上の高温で行りた場合には電極を形成す
べ吉シリコン表面からはみだして珪化物が形成されてし
まう。従って、最初低温でアニールを行った後、未度応
な高融点金属を除去するととによって電極を形成すべき
シリコン表面に自己整合して珪化物が形成される。温度
範囲を限定する理由は、40G’OKつ−てはイオン注
入して形成され先高融点金属とSiとの混合層がシリサ
イド化する最低限の温度、600℃は数十分程度の熱処
理時間ではみだして珪化物が形成されないための上li
I!温度であるためである・
この後、該珪化物層の抵抗串の減少及び注入されたイオ
ンの電気的活性化を目的とした800″O楓度以上の熱
処理が実施される。この熱処理をH2ガスを含んだ還元
性ガス雰囲気で行った場合には、前記低温熱処理によっ
て形成された珪化物の均一性や平滑性が失われてしま−
1これに伴ってピンホール等の欠陥が多数形成されるた
めのオーミック電極の形成には適さない。従って、非還
元性ガス雰囲気、例えば、窒素、不活性ガス、酸素、水
蒸気あるいはこれらの組合せたガス雰囲気または真空中
で800℃以上の熱処理を行うことが、珪化物の均一か
つ平滑な性質を維持する上で重要である。」
(8)明細書第12頁第1O行目のr Pn接合」とあ
るのを「νn接合」に補正する。
特許請求の範囲
電極を形成すべきシqコン基板表面に膜厚500A以下
の高融点金属層を形成する工程と、核高融点金属の上部
よりイオン注入を行った後、40Q−600℃の熱処理
を行な―、その後、未反応な高融点金属をエツチング除
去し、前記高融点金属のシリサイド層を前記露出シリコ
ン表面に選択的に形成するニーと、800℃以上Oi1
度で非還元性ガス雰囲気中で熱処理を行うニーと、前記
シリサイド表面の1部分にアルミニウム電極配線を接顎
させる工程とを含むことを特徴とする電子デバイスのオ
ーミッタ電極の製造方法。FIGS. 1(a) to 1(d) are schematic sectional views showing the manufacturing process of an embodiment of the present invention. 11...81 substrate, 12...river/oxide film, 13
・The old surface of Kameyama where the group/contact should be formed, 14...
・・・・Mo Ks 1s・・・・・・n”L 16・
...Mo silicide, '17... River/A1 electrode wiring. v-1 Merit Procedures Amendment (Import) 57.6.23 Showa Year, Month, Day, Director General of the Patent Office, 1, Indication of Case 1937 Patent Application No. 180
No. 518 No. 2, Title of the invention: Method for manufacturing an electronic device's automatic electrode 3, Relationship with the amended case: Applicant: 5-33-1-4 Shiba, Minato-ku, Tokyo, Agent: 108 Minato, Tokyo 5-37-8 Shiba, Sumitomo Mita Building, NEC Corporation (6591) Patent Attorney Susumu Uchihara Telephone Tokyo (0
3) 456-3111 (main representative) (contact information: NEC Corporation Patent Department) 5. Claims column of the specification to be amended. A column for detailed explanation of the invention of Meishu-sho. 6.11i Correct contents (1) Amend the Claims column as shown in the attached sheet. (2) In the fifth line of page t1M5 of the specification, "r Pn junction" is corrected to "rpn junction". (3) In the 5th line of page 8 of the specification, ``Ittatta'' is amended to ``Attata.'' Correct to. (5) In the first line of page 10 of the specification, the statement ``Heat treatment was performed at around 600°C'' was corrected to ``Heat treatment was performed at r400-60Q°C''. (6) In the fourth line of page 10 of the specification, the phrase "a step of heat treatment at a temperature of ℃ or higher" has been changed to "a step of heat treatment at a temperature of ℃ or higher in a non-reducing gas atmosphere." to correct. (7) Insert the following sentence in IIK of ``It is the one'' on page 10 of the letter, line 6. In the method of the present invention, after performing ion implantation, 400-6
A two-stage thermal process is carried out in which heat treatment is performed at a relatively low temperature of 00°C, followed by heat treatment at a temperature of 800°C or higher after removing unreacted high-melting metals, but this two-stage heat treatment is uniform. Moreover, it is extremely important in forming a smooth high melting point metal silicide in a self-aligned manner with respect to the silicon surface on which an electrode is to be formed. For example, the first annealing after ion implantation is
If the process is carried out at a high temperature of about 800° C. or higher, silicide will be formed protruding from the silicon surface on which the electrode is to be formed. Therefore, by first performing annealing at a low temperature and then removing any unsuitable high melting point metal, a silicide is formed in self-alignment with the silicon surface on which the electrode is to be formed. The reason for limiting the temperature range is that 40G'OK is the minimum temperature at which the mixed layer of high melting point metal and Si, which is formed by ion implantation, turns into silicide, and 600°C requires a heat treatment time of about several tens of minutes. In order to prevent the formation of silicide by protrusion,
I! This is because the temperature is - After this, heat treatment is performed at a temperature of 800"O or more for the purpose of reducing the resistance of the silicide layer and electrically activating the implanted ions. This heat treatment is performed at H2 If the process is carried out in a reducing gas atmosphere containing gas, the uniformity and smoothness of the silicide formed by the low-temperature heat treatment will be lost.
1. As a result, many defects such as pinholes are formed, making it unsuitable for forming ohmic electrodes. Therefore, heat treatment at 800°C or higher in a non-reducing gas atmosphere, such as nitrogen, inert gas, oxygen, water vapor, or a combination thereof, or in vacuum maintains the uniform and smooth properties of the silicide. It is important to (8) The phrase "r Pn junction" on page 12, line 1 O of the specification is corrected to "vn junction." Claims: A step of forming a refractory metal layer with a thickness of 500A or less on the surface of the Siqcon substrate on which electrodes are to be formed, and after performing ion implantation from above the core refractory metal, heat treatment at 40Q-600°C. After that, the unreacted high melting point metal is etched away, and a silicide layer of the high melting point metal is selectively formed on the exposed silicon surface, and Oi1 is heated at 800° C. or higher.
1. A method for manufacturing an ohmitter electrode for an electronic device, the method comprising the steps of: performing heat treatment in a non-reducing gas atmosphere at a temperature of 30° C.; and attaching an aluminum electrode wiring to a portion of the silicide surface.
Claims (1)
の高融点金属層を形成する工程と、該高融点金属の上部
よりイオン注入を行った後、600℃付近の熱処理を行
ない、未反応な高融点金属をエツチング除去し前記高融
点金属のシリサイド層を前記露出シリコン表面に選択的
に形成する工程と、800℃以上の温度で熱処理を行う
工程と、前記シリサイド表面の1部分にアルさニウム電
極配線を接触させる工程とを含むことを特徴とする電子
デバイ子のオーミック電極の製造方法。After forming a high melting point metal layer with a thickness of 500 mm on the surface of the silicon substrate on which electrodes are to be formed, and implanting ions from above the high melting point metal, heat treatment at around 600°C is performed to remove any unreacted metal. A step of etching away the high melting point metal and selectively forming a silicide layer of the high melting point metal on the exposed silicon surface, a step of performing heat treatment at a temperature of 800° C. or higher, and a step of etching aluminum on a portion of the silicide surface. A method for manufacturing an ohmic electrode for an electronic device, comprising the step of bringing electrode wiring into contact.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18051881A JPS5882520A (en) | 1981-11-11 | 1981-11-11 | Manufacture of ohmic electrode in electron device |
US06/657,080 US4551908A (en) | 1981-06-15 | 1984-10-02 | Process of forming electrodes and interconnections on silicon semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18051881A JPS5882520A (en) | 1981-11-11 | 1981-11-11 | Manufacture of ohmic electrode in electron device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5882520A true JPS5882520A (en) | 1983-05-18 |
Family
ID=16084657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18051881A Pending JPS5882520A (en) | 1981-06-15 | 1981-11-11 | Manufacture of ohmic electrode in electron device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5882520A (en) |
-
1981
- 1981-11-11 JP JP18051881A patent/JPS5882520A/en active Pending
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