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JPS5881972U - Laminated busbar - Google Patents

Laminated busbar

Info

Publication number
JPS5881972U
JPS5881972U JP1981177299U JP17729981U JPS5881972U JP S5881972 U JPS5881972 U JP S5881972U JP 1981177299 U JP1981177299 U JP 1981177299U JP 17729981 U JP17729981 U JP 17729981U JP S5881972 U JPS5881972 U JP S5881972U
Authority
JP
Japan
Prior art keywords
laminated busbar
conductive
ceramic dielectric
conductive layer
conductive adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981177299U
Other languages
Japanese (ja)
Inventor
浜田 義雄
佐藤 紘司
本郷 弘
Original Assignee
日立電線加工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電線加工株式会社 filed Critical 日立電線加工株式会社
Priority to JP1981177299U priority Critical patent/JPS5881972U/en
Publication of JPS5881972U publication Critical patent/JPS5881972U/en
Pending legal-status Critical Current

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Insulated Conductors (AREA)
  • Connection Or Junction Boxes (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の高静電容量積層母線の一例を示す側面図
、第2図はその分解斜視図、第3図は本考案高静電容量
積層母線の一実施例を示す分解斜視図、第4図はセラミ
ック誘電体と導電層との沿面距離と板状導体間の導通の
発生の関係を示した特性曲線である。 1.2:板状導体、3,4:端子、5:セラミック誘電
体、6,7:導電層、8,9:導電性接着剤。
FIG. 1 is a side view showing an example of a conventional high capacitance laminated bus bar, FIG. 2 is an exploded perspective view thereof, and FIG. 3 is an exploded perspective view showing an embodiment of the high capacitance laminated bus bar of the present invention. FIG. 4 is a characteristic curve showing the relationship between the creepage distance between the ceramic dielectric and the conductive layer and the occurrence of conduction between the plate-shaped conductors. 1.2: Plate conductor, 3, 4: Terminal, 5: Ceramic dielectric, 6, 7: Conductive layer, 8, 9: Conductive adhesive.

Claims (1)

【実用新案登録請求の範囲】 少なくとも2枚が互いに離間されて配置された板状導体
と、その間に設けられた両表面に導電層がコーティング
されたセラミック誘電体との両者を、導電性接着剤で接
着一体化して成り、該導電層はセラミック誘電体の幅及
び長さよりも少くとも0.4m狭く施されていると共に
、導電性接着剤は導電層の中央部に帯状に塗布されて構
成され。 ていることを特徴とする積層母線。
[Claims for Utility Model Registration] A conductive adhesive is used to bond at least two plate-shaped conductors spaced apart from each other, and a ceramic dielectric material provided between them with conductive layers coated on both surfaces. The conductive layer is formed to be at least 0.4 m narrower than the width and length of the ceramic dielectric, and the conductive adhesive is applied in a strip at the center of the conductive layer. . A laminated busbar characterized by:
JP1981177299U 1981-11-28 1981-11-28 Laminated busbar Pending JPS5881972U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981177299U JPS5881972U (en) 1981-11-28 1981-11-28 Laminated busbar

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981177299U JPS5881972U (en) 1981-11-28 1981-11-28 Laminated busbar

Publications (1)

Publication Number Publication Date
JPS5881972U true JPS5881972U (en) 1983-06-03

Family

ID=29971051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981177299U Pending JPS5881972U (en) 1981-11-28 1981-11-28 Laminated busbar

Country Status (1)

Country Link
JP (1) JPS5881972U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943764B1 (en) 1994-04-22 2005-09-13 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for an active matrix display device
US7145173B2 (en) 1994-04-22 2006-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit
US7223996B2 (en) 1992-05-29 2007-05-29 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
US7489367B1 (en) 1991-03-26 2009-02-10 Semiconductor Energy Laboratory, Co., Ltd. Electro-optical device and method for driving the same
US7569408B1 (en) 1991-03-06 2009-08-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7569408B1 (en) 1991-03-06 2009-08-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US7489367B1 (en) 1991-03-26 2009-02-10 Semiconductor Energy Laboratory, Co., Ltd. Electro-optical device and method for driving the same
US7223996B2 (en) 1992-05-29 2007-05-29 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
US6943764B1 (en) 1994-04-22 2005-09-13 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for an active matrix display device
US7145173B2 (en) 1994-04-22 2006-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit
US7166862B2 (en) 1994-04-22 2007-01-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit
US7477222B2 (en) 1994-04-22 2009-01-13 Semiconductor Energy Laboratory Co., Ltd. Redundancy shift register circuit for driver circuit in active matrix type liquid crystal display device

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