JPS5870576A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To allow the fine formation of an element, by leading out ohmic electrodes from inside the aperture of an insulating film provided on an active layer onto the insulating film resulting in a contactless constitution with a substrate. CONSTITUTION:An SiO2 film 11 is formed on the semi-insulating substrate 1 constituted of GaAs, next the aperture 12 is provided, and the active layer 12 is formed on the aperture 12 part. Next, the film 11 is once removed, an SiO2 film 13 is formed again, and an aperture 14 is provided at the position approximately the same as that of the aperture 12. Next, a gate electrode 15 is formed in the aperture 14. Next, N<+> regions 16, 16' as source and drain regions are formed on the part of the layer 2 wherein the surface is exposed. Next, the film 13 is removed, and an SiO film 17 is formed on the substrate 10. Next, the film 17 is selectively removed, and apertures 18, 18' are formed on the regions 16, 16'. Source and drain electrodes 19, 19' which take ohmic contact with the regions 16, 16' exposed in the apertures 18, 18' and are led out to the film 17 are formed. Thus, the margin for the positioning to form a contact electrode is unnecessitated, and accordingly microminiaturized element can be formed.

Description

[Detailed description of the invention]

The present invention relates to semiconductor devices, and particularly to improvements in FETs made of compound semiconductors. Conventionally, FETs made of GaAs have the structure shown in FIG. 1, in which a semi-insulating substrate 1 made of GaA3 doped with chromium (Or) is doped with silicon (Sl). Active layer 2 made of n-type GaA3
is formed into a mesa shape, and on top of that, aluminum (AI),
Alternatively, titanium (T1) - platinum (Pt) - aluminum (Au) are sequentially laminated to form a nine-gate electrode 5, and a gold-germanium alloy (
Source and drain electrodes 4 and 4' made of laminated layers of AuGe) and gold (Au) are formed. These gate electrode 3 and source and drain electrodes 4, 4' are all led out onto the active layer 2 and onto the semi-insulating substrate 1, forming wiring or lead-out electrodes. AI or T1 in the gate electrode Wi3 is GaAs
AuGe ij n ill GaA to form the V3 contact with the substrate and also the source and drain electrodes 1i4
It is an ohmic contact material to the s-substrate. Therefore, it was considered that there would be no problem even if both of them were led out and disposed on the surface of the semi-insulating substrate 1 as described above. However, in reality, in the above structure, electrons or holes are injected into the semi-insulating substrate! - Occasional characteristic instability phenomenon (substrate bias effect) occurs, which adversely affects the electrical characteristics of the semiconductor device. Therefore, a rounding structure shown in FIG. 2 has already been proposed to solve this problem. This structure connects the source and drain electrodes to the contact electrodes 11K 5 , 5' and the lead wiring 6.
6'. That is, the contact electrodes 5, 5' are formed only on the active layer 2, and the lead wiring 6
．． 6' is selectively formed on the insulating film 7 having an opening above the contact electrode 5.5', and is connected to the contact electrodes 5 and 5', respectively, within the opening. By adopting such a structure, the occurrence of the substrate bias effect described above was prevented, but on the other hand, alignment margin must be provided for both the contact electrode 5.5' and the insulating film 7 when forming the opening. Therefore, it is difficult to miniaturize and increase the density of elements. This problem occurs not only in source and drain electrodes, but also in all electrodes that form ohmic contact, such as resistor electrodes formed on the surface of a semi-insulating substrate, which are collectively referred to as ohmic electrodes. An object of the present invention is to provide an improved structure of an FET made of a compound semiconductor that can solve the above female point and miniaturize the device. This is achieved by leading out onto the insulating film from within the opening of the insulating film and making no contact with the insulating or insulating substrate. An embodiment of the present invention will be described below with reference to a cross-sectional view of the main parts in FIG. As shown in Fig. 3), a silicon dioxide (S10□) film 11 is formed to a thickness of approximately 4000 μm on a semi-insulating substrate 1 made of GaA3 by chemical vapor deposition (CYD). Next, this is selectively removed to form an opening 12, and silicon (Sl) is injected into the opening 12 by ion implantation.
was injected and heated at a temperature of about 850 ['C] for about 15 minutes.

[minutes] Apply Annie μ to obtain a dose of 1X lo' [ag-”
], an n-type active layer 2 having an average oblique range of about 500 [X] is formed. Note that 10 indicates a nine-element substrate formed as described above. Next, the above Sin, $ 11 is removed once, and the thickness is about 6000 mm again as shown in the same figure (towards).

['A]08102
A film 13 is formed and selectively removed to provide an opening 14 at approximately the same position as the opening 12. Next, a gate electrode 15 made of a mixed metal of TiW and 81 is formed in the opening 14 using a sputtering method, a reactive ion etching method, or the like. Note that since the gate electrode 15 made of 'r1w-sx forms a Schottky contact with GaAs, it may be extended to the outside of the active layer 2, that is, to the surface of the semi-insulating substrate 1, although not shown. Next, using the upper E3sio2 film 16 and the gate electrode 15 as masks, Sl is implanted into the exposed surface of the active layer 2 by ion implantation to form n regions 16 and 16'. The dose of the n+ type region 1616' is approximately 1.7X
10"[aM-"], average oblique range approximately 1500 [X]
shall be. The fI+ type regions 16 and 16' are source and drain regions, and according to the manufacturing process described above, the gate electrode 15
It is formed by self-alignment with. Note that the process up to this point is no different from the conventional process. Next, the above Sin,@15 is removed, and as shown in FIG.
0

Form to a thickness of [ku]. Next, as shown in the same figure, the sto and s 17' are selectively removed to form source and drain regions 16° and 16'.
An opening 18.18' is provided at the top. Then, by vapor deposition method, ion milling method, etc., about 20
0[X] thick AuGe alloy layer and about 5ooo on top of it
(selectively depositing an Au layer with a thickness of about 450 il)
By performing heat treatment at a temperature of ["O], the source and drain regions 1 are exposed in the openings 18 and 18'.
6.16' and in ohmic contact with SiO! Membrane 1
7 and the source and drain voltages 41ii19i9
' to form. The semiconductor device according to the present invention obtained as described above is similar to the conventional device.

The contact electrode 5.5' is removed from the ohmic electrode consisting of the contact electrode 5.5' and the lead wires 6, 6', including the lead wires 6, 6' in [See Figure 2].
The electrode also serves as a contact electrode. By adopting such a structure, the semiconductor device of the present invention does not require a positioning margin for forming the contact electrodes 5, 5', and the element can be miniaturized. For example, gate electrode 15. The dimensions of the openings 18 and 18' are each 2

[μm], and the alignment margin is 2 each.

[μm]
In this case, the width of the active layer is 26 in the conventional device.

[μ
m] In this example, 18

[μm], which is 70

[%] Slightly reduced. Note that the present invention is not limited to the above embodiment,
Furthermore, various modifications can be made. For example, in the above-described embodiment, the insulating film 17 was formed to cover the gate electrode 15, but this was reversed, and as shown in FIG.
In the same manner as above, the active layer 2 is
The gate may have a structure in which it is brought into contact with the insulating film 17 from inside the opening, and the structure of the gate is not limited to the present invention. The type of compound semiconductor used, gate electrode material, ohmic electrode material, manufacturing method, etc. can be selected as appropriate. As explained above, according to the present invention, it is possible to miniaturize the pattern of a semiconductor device, and therefore, it is possible to miniaturize and increase the density of a compound semiconductor integrated circuit device.

[Brief explanation of drawings]

FIGS. 1 and 2 are ninth sectional views of essential parts for explaining a conventional semiconductor device, and FIGS. 6 and 4 are sectional views of essential parts showing one embodiment and other modifications of the present invention. In the figure, 1 is an insulating substrate or a semi-insulating substrate, 2 is an active layer, 15 is a gate electrode, 16.16' is a source and drain region, 17, 711 is an insulating film, 18.18' is an opening, 19. 19' indicates an ohmic electrode. Figure 3 Figure 4

Claims (1)

[Claims] On an element substrate comprising an insulating substrate or a semi-insulating substrate and an active layer made of a compound semiconductor selectively formed on the surface thereof, a gate electrode that forms a Schottky contact with the surface of the active layer, and the active layer. an insulating layer having an opening on its surface;
A semiconductor device comprising: a 9-ohmic electrode that forms ohmic contact with the active layer within the opening and is led out onto the insulating film.